Search Engine

Static Expression

Add Question

6 Threads found on Static Expression
Hello, Is this allowed inside Xilinx ISE : generic map (record1.field1'length) ?? Previously I have defined record: type test_record is record field1 : std_logic_vector(31 downto 0); field2 : std_logic_vector(31 downto 0); end record; constant record1 : test_record := ((others => '0'),(others => '0')); I get this error
Hi, I get the following Modelsim error when compiling my design for simulation: "# ** Error: tx_and_replica.vhd(362): Actual (function call "to_sfixed") for formal "i_x" is not a globally static expression." The relevant code snippets are: 1) Port mapping: Line 362 is the s_tx_tmr conversion to signed fixed. U_ITPL_TTL_HIGH: li
As godfreyl noted, the motor torque is just that needed to overcome any static friction plus how fast to want to accelerate the rotor. As the rotor speeds up, then the motor need to provide enough torque to overcome the moving friction plus the air drag from the blades.
Hi, I'm working one generating a VCCS in finesim. The code is as follows : Videal ideal 0 1 rpolyres ideal 0 50k gin_current IN OUT pwl(1) IN OUT 0 0 0.1 0 0.2 'i(videal)' Howere, I always get an error saying 'ERROR! variable in static expression' I checked the .sp file and find that it is the 'i(videal)' that causes this pro
I'm getting the following error when compiling in ModelSim: Array type case expression must be of a locally static subtype. The error points to the first part of the case statement in the following code: library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity amplitude_lookup is generic (
answer is yes and no. use temporal expression to do that. assertions are two kind (static - without simulation ) -which is not possible in specman and (dynamic - while simulation ) - which is very much possible through temporal checks /.ue