1000 Threads found on edaboard.com: Static Expression
I get the following Modelsim error when compiling my design for simulation:
"# ** Error: tx_and_replica.vhd(362): Actual (function call "to_sfixed") for formal "i_x" is not a globally static expression."
The relevant code snippets are:
1) Port mapping: Line 362 is the s_tx_tmr conversion to signed fixed.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-18-2014 06:24 :: zermelo :: Replies: 1 :: Views: 335
In xilinx spartan2 there are block RAMs which is defined in Verilog. I am writing a VHDL code using these block RAMs and calling these RAMs as a component and port mapping accordingly. While simulating my VHDL code in Modelsim i am getting a following error
"Actual (prefix expression) for formal "web" is not a globally static expres
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-21-2008 11:07 :: vijayanand_ME :: Replies: 2 :: Views: 1781
I'm working one generating a VCCS in finesim.
The code is as follows :
Videal ideal 0 1
rpolyres ideal 0 50k
gin_current IN OUT pwl(1) IN OUT 0 0 0.1 0 0.2 'i(videal)'
Howere, I always get an error saying 'ERROR! variable in static expression'
I checked the .sp file and find that it is the 'i(videal)' that causes this pro
Analog Circuit Design :: 11-12-2013 13:36 :: nozombie :: Replies: 0 :: Views: 299
I'm getting the following error when compiling in ModelSim:
Array type case expression must be of a locally static subtype.
The error points to the first part of the case statement in the following code:
entity amplitude_lookup is
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-21-2009 07:05 :: dohzer :: Replies: 0 :: Views: 2949
Here is one more presentation about static tiiming anaysis
ASIC Design Methodologies and Tools (Digital) :: 12-13-2002 06:42 :: avinashr :: Replies: 4 :: Views: 3086
The idea with polyfit sounds great.
Unfortunatelly I don't know the range.
To be more specific here is the code that I try to optimize:
static float EvaluateC_PF(DEB_PARAM*deb_param,float RD,BOOL first_call,void* cache_buf)
A = pow((19000.0*deb_par
PC Programming and Interfacing :: 01-20-2003 10:56 :: suiram :: Replies: 9 :: Views: 1882
some material about PSRAM
Interfacing Toshiba Pseudo-static RAM with Toshiba MIPS RISC and Motorola PowerPCTM Processors:
Including a performance comparison between Toshiba Pseudo-static RAM and Low-Power SRAM
PC Programming and Interfacing :: 02-01-2003 11:29 :: jamesz :: Replies: 2 :: Views: 1982
I have PINE D'Music sm300t mp3 player. It doesn't has anti shock protection. But after opening it you can find there some memory - W26L010A 64K × 16 HIGH-SPEED CMOS static RAM. Can somebody tell me what for it is there? Is it anti shock but not activated?
THX for info.
Professional Hardware and Electronics Design :: 03-18-2003 12:46 :: Bizum :: Replies: 0 :: Views: 712
I'd like to simulate the 3-D static (or change slowly) electric field
for the device. Some electrodes will put into the medium and I want to
get the electric field data in 3 dimension.
There are many software for EM simulation. Can you give me some idea
which one is suitable for this task? Thanks in advance.
Electromagnetic Design and Simulation :: 03-28-2003 12:17 :: xinyin :: Replies: 7 :: Views: 2938
I need a cheap and reliable method/sensor to measure
line tension (force) in a static line. Can be inserted into the line
path. Range up to 200 kgf.
Robotics and Automatics Forum :: 10-23-2003 07:29 :: cosmin :: Replies: 3 :: Views: 2174
In my ModelSim testbench, I'm trying to drive a 16-bit bus with the results of a tcl expression. For example:
ModelSim complains that -7568 is unacceptable. Well yes, "force" expects a format such as -16'd7568 or 1110001001110000. What do I add to my expression to do the necessary format conversion?
PC Programming and Interfacing :: 11-05-2003 23:47 :: echo47 :: Replies: 4 :: Views: 1733
does anybody have simplified analytical expression of MOS varactors ?
I've read many articles about them and the only article I found was one of Thomas Lee's group about accumulation mode, where some analytical expressions were given but no derivation of them what makes it difficult to read.
Analog IC Design and Layout :: 06-04-2004 08:29 :: CTT :: Replies: 2 :: Views: 1672
hI, I HAVE TO INTTERFACE A static RAM USING A DATA BUS AT 16 BITS.
IS CORRECT THAT I USIGN THIS MAP ?
A1 ------------------> A0
A2 ------------------> A1
Microcontrollers :: 06-10-2004 11:41 :: firstname.lastname@example.org :: Replies: 4 :: Views: 926
When using Cute ftp Server, do I need a static IP from my internet service provider or register for a domain name?
How do I getr an address which I give people?
Software Problems, Hints and Reviews :: 07-07-2004 05:55 :: bimbla :: Replies: 1 :: Views: 830
In "ESD in silicon integrated circuits", A.Amerasekera & C. Duvvury (p.12 - ) there is a solution for LCR curcuit ( ) :
i = Vc*Cc*pow(w0,2)/sqrt(pow(a,2)-pow(w0,2))*exp(-a*t)*sinh(sqrt(pow(a,2)-pow(w0,2))*t)
with a = R/(2*L1) and w0 = 1/sqrt(L1*Cs) and a>w0.
So, this expression give st
Analog Circuit Design :: 08-26-2004 04:12 :: Phantom :: Replies: 0 :: Views: 739
You could get one of these cheap WLAN Routers with embedded Linux (about 90EUR).
If router comes with a USB port (like Asus WL-500G(x)) for attaching an external USB drive, you can use this as a server.
There are also quite a few NAS (network attached storage) devices (from Asus, Linksys, ...), which are also Linux based and therefore could also
Hobby Circuits and Small Projects Problems :: 08-31-2004 11:15 :: mip :: Replies: 8 :: Views: 1492
I have some basic doubts regarding preparing input information for static TIMING ANALYSIS,
1. HOW TO CALCULATE THE SETUP AND HOLD TIME FOR DESIGN ,
2. TO FIX THOSE SETUP AND HOLD TIME SHOULD I USE DATAS FROM THE LIBRARY .
3. HOW TO CALCULATE THE RISE TIME AND FALL TIME VALUES FOR THE CLOCK SIGNAL
4. HOW TO CALCULATE THE CLOCK LATENCY FOR
ASIC Design Methodologies and Tools (Digital) :: 09-28-2004 06:39 :: au_sun :: Replies: 1 :: Views: 659
In the paper:Analysis and design of Injection locked LC dividers for quadrature generation,JSSC 2004. I can not get the expression(please see the attachment) for the impedance of LC element.
Woul you please give me any advice?
Thank you very much.
RF, Microwave, Antennas and Optics :: 11-22-2004 06:56 :: trashbox :: Replies: 1 :: Views: 688
I am affraid you ip is given by your provider so unless you pay them you can not have a static address.
Software Problems, Hints and Reviews :: 01-04-2005 07:04 :: geconom :: Replies: 1 :: Views: 737
Here is a paper on a review of electrostatic measurement techniques:
One company that makes this stuff is
They have electrostatic volt meters, charge plate monitors, and similar equipment for electrostatic measurement and control.
Electronic Elementary Questions :: 01-15-2005 12:18 :: DoctorProf :: Replies: 3 :: Views: 957
what does it mean by static drive? 1/2, 1/4 duty cycle driving?
Microcontrollers :: 01-17-2005 22:47 :: banh :: Replies: 2 :: Views: 1121
Dynamic means the internal states in a circuit change, then you need input vectors to drive the circuit.
static means the internal nodes keep unchange in the timing analysis process.
ASIC Design Methodologies and Tools (Digital) :: 01-22-2005 03:16 :: ymli :: Replies: 4 :: Views: 2296
I don't know whether if it's the correct place to place this. I would like to ask what is the maning of closed form expression. I notice this term in some RF books but it seems to me that its a math enquiry so I post this here
Mathematics and Physics :: 02-21-2005 09:48 :: evoplus :: Replies: 5 :: Views: 5290
Is there any software suitable for the simulation to static electric field?
Electromagnetic Design and Simulation :: 02-24-2005 20:08 :: hellotxn :: Replies: 3 :: Views: 2731
Is it possible to analyze the static electric field with hfss?
Electromagnetic Design and Simulation :: 02-25-2005 04:19 :: hellotxn :: Replies: 1 :: Views: 1034
First, I see several C mistakes. Maybe this is what you want:
static int a=5;
if (--a > 0)
That function calls itself reentrantly four times while decrementing 'a'. It prints "0" just before it returns each time, so the final output i
PC Programming and Interfacing :: 02-26-2005 05:37 :: echo47 :: Replies: 5 :: Views: 794
I was trying to derive the Thermal Noise Current expression for the MOS. Could anyone give me a reference as to where I can find it, or how to derive it? I guess it must be similar to the derivation of Cgs in Saturation.
I am talking about the expression
Idn? = 4KTγ gm where γ=2/3
Analog Circuit Design :: 03-03-2005 23:51 :: aryajur :: Replies: 2 :: Views: 1211
People always tell me to avoid using latch in a design. This is due to the difficulties tht I will face later during my static timing analysis.
So far, I havent done the STA on latch based design before. Now, can someone pleeease enlighten me.
Why is it so hard to do STA on latch design?? What are the difficulties and the right method
ASIC Design Methodologies and Tools (Digital) :: 03-16-2005 21:39 :: no_mad :: Replies: 1 :: Views: 1596
hi all is there is any equivalent to this static ram
thanks for cooperation
Professional Hardware and Electronics Design :: 03-16-2005 23:04 :: scorpionss22 :: Replies: 1 :: Views: 1007
You should check the latest GSM for GSM 05.05 (Radio transmission and reception)...
Actually sensitivity levels for MS's are varying between -102 and -104dBm for different GSM implementations (850, 900, 1800 etc)
For static sensitivity's BER see Table 1 in Section 6...
RF, Microwave, Antennas and Optics :: 03-18-2005 19:19 :: mogwai :: Replies: 1 :: Views: 3207
I am currently designing R2R 8-bits DAC. Now I want to simulate the DAC static performance i.e. offset error, gain error, INL and DNL. What I did was, I generated an ideal 8-bit DAC and compared the transfer slope to the actual DAC (ideal DAC slope vs actual DAC slope). From this I can directly measure INL/DNL/Offset?Gain Error. How
Analog IC Design and Layout :: 03-21-2005 22:41 :: snoop835 :: Replies: 8 :: Views: 2233
is it illegal to use 'z' value in expression, in synthesis point of view?
and in any form inside a clocked always block?
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-07-2005 10:45 :: Prasanna Kumar :: Replies: 4 :: Views: 4192
any one having some materials on static TIMING ANALYSIS....some books or pdf or links
Electronic Elementary Questions :: 06-08-2005 06:01 :: ikru26 :: Replies: 3 :: Views: 658
u can search it in this forum:
ASIC Design Methodologies and Tools (Digital) :: 06-21-2005 03:27 :: dolby.yang :: Replies: 3 :: Views: 1332
can somebody tell me how to tell the difference between static and dynamic system.....pls provide examples as i am really new in this subject...
Digital Signal Processing :: 07-16-2005 10:42 :: nafaiz :: Replies: 1 :: Views: 1216
what is static noise margin
pls xplain with diag
Electronic Elementary Questions :: 08-06-2005 17:57 :: aman :: Replies: 0 :: Views: 1028
For more information, refer to Sedra & Smith, "Microelectronic Circuits" on small-signal amplification, single transistor amplifier, emitter degeneration.
A bypass capacitor in parallel with a emitter resistor Re sees its purpose in AC conditions. Capacitor in DC is an open-circuit. Thus static current Icq only flows throught emitter resistor in
Electronic Elementary Questions :: 08-17-2005 03:13 :: SkyHigh :: Replies: 25 :: Views: 2763
hi, anybody can give me an explanation of SOP expression coverage? I got this warning message from IUS55 coverage
ncelab: *W,COVSEC: (/export/home/xxx/prj/IP/uart/rtl/uart_dpll.v,115|22): SOP expression evaluates to a constant: not checked
thanks a lot!:D
ASIC Design Methodologies and Tools (Digital) :: 08-22-2005 01:16 :: Arnold :: Replies: 3 :: Views: 2791
What are static 7-segment displays?
Electronic Elementary Questions :: 08-23-2005 16:33 :: coolchip :: Replies: 2 :: Views: 1760
We often encounter the term "Quasi static" analysis in EM. What exactly does it mean ? Can anyone clarify on this ?
Electromagnetic Design and Simulation :: 09-29-2005 04:27 :: svarun :: Replies: 10 :: Views: 19053
You can find all kinds of math expression and semantics from the website below:
Software Links :: 09-30-2005 07:38 :: ytcheng0117 :: Replies: 1 :: Views: 616
Can any one tell which are the positives and negatives of these types CMFB for diferential amplifgiers:
1. Switched capacitor CMFB.
2. static CMFB.
Analog IC Design and Layout :: 10-07-2005 02:20 :: tyanata :: Replies: 2 :: Views: 1090
Can any one provide me some scenario's how to fix the setup and hold time violations. any material on static timing analysis
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-13-2005 02:29 :: noorullam :: Replies: 4 :: Views: 1078
I'm trying to use matlab for the first time, and have trouble typing the following
expression. There's a convolution in it and the Phi fuction is the standard distribution function.
I need this because I got the task in class to calculate the gradient of this
expression by using the first some significant z values.
Thank you for you
PC Programming and Interfacing :: 10-14-2005 19:23 :: Thommer :: Replies: 0 :: Views: 707
I've modelated a structure with a microstrip in hfss and found magnitude of the E-field in several points. Now want to compare this magnitudes with the theoretical ones.
So can anyone advise me an easy and convenient analytic expression to calculate the magnitude of the E-field in the exact point.
Thanks in advance!
Electromagnetic Design and Simulation :: 10-26-2005 00:38 :: Zhariks :: Replies: 6 :: Views: 998
I was asked in a interview, but I am not familar with Primetime.
"What is timeborrowing related to static timing anaylsis in Primetime?"
Any suggestions will be appreciated!
ASIC Design Methodologies and Tools (Digital) :: 10-27-2005 05:10 :: davyzhu :: Replies: 12 :: Views: 4281
dynamic CMOS logic - more or less like pseudo nmos/ generic logic. only dynamic power dissipation like pdyn= CL*Vdd^2.
well static CMOS and Dynamic CMOS logics have their advantages and disadvantages.. if you go in for dynamic logic.. cascading is not possible as in evaluation stage the transition from 0-1 doesnt occur as PDN would be disabled.
ASIC Design Methodologies and Tools (Digital) :: 11-11-2005 11:29 :: arunragavan :: Replies: 7 :: Views: 12657
I hope everyone are fine. I am an EE student and have been asked to Design a 32-bit static CMOS Adder with Minimum Area Delay-Squared Product. Well I am looking for some ideas and help on getting me started. Any kind help would do a lot to me.
SOME NOTES GIVEN TO ME.
The goal is to design an unsigned 32-bit adder using static
Analog IC Design and Layout :: 11-11-2005 01:01 :: mailkit :: Replies: 2 :: Views: 1614
I need a fine analytical expression for designing fractal antennas(sierpinski gasket/carpet). Do anyone have these design equations??
RF, Microwave, Antennas and Optics :: 11-25-2005 23:22 :: arunkumar :: Replies: 7 :: Views: 1186
How can i build Ionizing Bars for static elimination?.
Hobby Circuits and Small Projects Problems :: 12-06-2005 13:16 :: Moof :: Replies: 0 :: Views: 576