6 Threads found on edaboard.com: Static Expression
Is this allowed inside Xilinx ISE : generic map (record1.field1'length) ??
Previously I have defined record:
type test_record is record
field1 : std_logic_vector(31 downto 0);
field2 : std_logic_vector(31 downto 0);
constant record1 : test_record := ((others => '0'),(others => '0'));
I get this error
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-22-2016 08:40 :: ZoraNustra :: Replies: 6 :: Views: 184
I get the following Modelsim error when compiling my design for simulation:
"# ** Error: tx_and_replica.vhd(362): Actual (function call "to_sfixed") for formal "i_x" is not a globally static expression."
The relevant code snippets are:
1) Port mapping: Line 362 is the s_tx_tmr conversion to signed fixed.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-18-2014 06:24 :: zermelo :: Replies: 1 :: Views: 1929
As godfreyl noted, the motor torque is just that needed to overcome any static friction plus how fast to want to accelerate the rotor. As the rotor speeds up, then the motor need to provide enough torque to overcome the moving friction plus the air drag from the blades.
Analog Circuit Design :: 12-10-2013 12:12 :: crutschow :: Replies: 22 :: Views: 1274
I'm working one generating a VCCS in finesim.
The code is as follows :
Videal ideal 0 1
rpolyres ideal 0 50k
gin_current IN OUT pwl(1) IN OUT 0 0 0.1 0 0.2 'i(videal)'
Howere, I always get an error saying 'ERROR! variable in static expression'
I checked the .sp file and find that it is the 'i(videal)' that causes this pro
Analog Circuit Design :: 11-12-2013 13:36 :: nozombie :: Replies: 0 :: Views: 697
I'm getting the following error when compiling in ModelSim:
Array type case expression must be of a locally static subtype.
The error points to the first part of the case statement in the following code:
entity amplitude_lookup is
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-21-2009 07:05 :: dohzer :: Replies: 0 :: Views: 4327
answer is yes and no.
use temporal expression to do that.
assertions are two kind
(static - without simulation ) -which is not possible in specman
(dynamic - while simulation ) - which is very much possible through temporal checks
Microcontrollers :: 06-09-2006 04:05 :: ue :: Replies: 2 :: Views: 1910