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26 Threads found on edaboard.com: Surianova
thanks a lot surianova I simulated but it wase given me 1 poit In 0 6 0 ac 1 .ac dec 1 1 1.2g .probe V(6) why? should input source shrt circuit?
Hi, I am designing an amplifier. I found the PSRR in DC is only -38dB in typ. I am trying to check out why it has so low PSRR. Anyone pls. shed some light on it? Thanks in advance it depend on your open loop gain of your opamp, try to increase it, you will get better psrr
use smaller capacitor for frequency compensation. and use buffer to isolate the load from the bandgap circuit Could you please elaborate on how using smaller compensation capacitor can improve PSRR? thanks i use 2 pF cap for frequency compensation. i can acheive -35dB at 1 Mhz.
Hi surianova, You can design a Gm-C filter with a cut frequency 1kHz. Actually, I am designing a Gm-C filter with a cut frequency equals to 1.92kHz and it is successeful. So, good work. thank you.. what is Gm of the OTA? is it need to be very low?
Hi surianova, Yes in this circuit u very much need the startup circuit... This circuit has two stable states one with zero current and other one with defined branch currents... and the second state is desired. So to pull it away from first state and pushe it into second one we need to inject some current into its branches
hi all! is it important for diode in bandgap with 8:1 ratio for common centroid to have dummy surround it? for resistor of course we put dummy. How about diode? Usually I use bipolar transistors as diodes without dummy elements.
Hi surianova The current I in the circuit below have the the value independent to the supply voltage. You can mirror it (using the NMOS transistors) and use it as a current source. to make it
To JPR: Hi, could you please explain about what dose the "accuracy more than about 8-bit using the Vref" mean? And why should a bandgap circuit has bandwidth? And why should the change in load affect a bandgap circuit? I think in most circuits they are quite independent from each other. To surianova: Hi, why do u simulate the noise fr
thank you all! But on the contrary, my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA). The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is co
hi! What is the advantage of active filter over passive filter and why we need active filter ? Thanks active filter can be implemented in IC. some components in passive filter can not be implemented easily. for example inductor.
hi all. I am using cadence to simulate the resistor but i use the ideal resistor. When i look at the property of the resistor, it got TC1 & TC2. Why got 2 TC and what is the unit ? is it in ppm/ ?K? Hi Suria, Some resistors have 2 TC (ie unsalicided poly and island). If you plot R vs T of that particular resistor, u w
Hi surianova! Putting a resistor to sink 1mA can only give an approximate result as the load capacitance is not modelled, which is critical in finding out frequency response. It would give a better response than what you would get with inverters connected. Giri
Hi surianova, The parameters on which the sensitivity depends from sensor to sensor. Like if i am using Platinum RTD the sensitivity depends on the input constant current to the resistance (RTD). Sensitivitycan be increased by increasing input current or resistance. If we want a general control then varing the gain of the amplifier in
surianova wrote: normally how much the ESR for capacitor on chip? Generally the value of ESR is on the order of mΩ.
Hi V_C, I have read a few journals, mentioning that putting a Caps (no matter internal or external) will help in high freq noise rejection in a LDO design for both NMOS and PMOS pass transistor. In the forum by surianova, you mentioned that for NMOS pass transistor , it is not necessary to have caps as the output impedance is low and this if you
Hi surianova, Migrating from CMOS to Bipolar is a good choice especially when you are about to design a high frequency circuits. Even in CMOS we can achieve to design for 10Gbps but with the help of On chip inductor where it is not a good choice for designers when it comes to chip size. I think that in order for you to understand about Bipolar d
This is because normally opamp has compensation capacitor which will slow down response time of the output or the rising/ falling of the output. As comparator, you no need it because it is a open loop system. Correct. The most popular OA, the 741, had a version without the compensation capacitor (if I'm not wrong, it was
Hi surianova, As you said, in saturation region current , Ids will be constant for even Vds change, but since the existence of short channel effect/lambda effect, anyhow you won't flat curve. So, the value of Ron could be measureable as I stated. Other's opinion are welcome. Correct me if im wrong. Thanks surianova. The slope which gives, &
hi all, How to measure Input referred noise for Transimpedance amplifier using Cadence? Thanks surianova
What is the criteria can be used to choose for the best design project? surianova
Hi all, I have a question how to check this CMFB loop? 1. is it the open loop gain (Vocm+ minus vocm-)/vicm? 2. How about phase margin, is it phase for Vocm+ minus phase for vocm- ? 3. Can break the loop at point A instead? Thanks in advance.. surianova
you can connect the ring oscillator through a NMOS to the power supply. By adjusting the gate volatge of the NMOS, you can control the frequency. surianova
Hi In a circuit, for example opamp, how we can know a zero is exist at the RHP or LHP without much calculation. I mean something very fast, from the cuicuit, you know where is the zero at RHP or LHP. surianova
Hi surianova: How do you justify the speed of a signal path?. Is it in propotional to the delay time of the circuitry? . Thank You Rgds
Hi Why people always 3.3 vpower supply and not 3v? Is it any reason for that? Just curious to know that. Suria ---------------------------------------------------------------------------------- i think it's based on two reason: 1. most of the process use vdd/vcc 3.3v not 3v. 2. on the board level design, mo
Hi all, What is the advantage of folded cascode opamp compare to telecospic cascode opamp and olso its application? Thanks in advanvce. Hi, the big advantage of a folded cascode is its larger outputswing. And as you know the more signal range, the higher the SNR. Unfortunately you have more branches between Vdd a