1000 Threads found on edaboard.com: Switch Verilog
can you correct my code... i dont how to use switch with the clock. so that when i on the swicth the clock start j is start counting. plez help me.
output reg keluar,
// reg result = 6'b000000;
reg en = 1'b0;
reg i = 0;
integer j= 0;
always @ ( posedge clk)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-30-2010 05:19 :: alierossi :: Replies: 3 :: Views: 1045
Hi,I need a verilog code for a banyan switch...
if there are two inputs say x1 and x2
and two outputs say y1 and y2
there is a select line s
for s=0 i must send the data through upper port
for s=1 i must send data through lower port.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-06-2011 13:58 :: prasan61 :: Replies: 4 :: Views: 1652
I have an issue with trying to figure out how to implement a simple switch (as in OPEN or CLOSE circuit) in verilog.
Some background: I have a device that takes user button presses (mostly a capacitive switch) and I have a design that will automatically "press buttons" given certain conditions. The plan I have is to make a small module (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-02-2012 17:53 :: fysloc :: Replies: 0 :: Views: 456
Hi, im new in verilog coding, i need help for the 2-line LCD display in Altera DE2 board
I want to write a coding when switch 1 on, it will change the text in display and address value, and for the switch 2
I have compiled the coding and found some error, so someone help me solve the problem?
always @(posedge CLOCK_50 or negedge SW)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-09-2012 11:11 :: yamcake01096 :: Replies: 1 :: Views: 1127
I have ap roblem with a entlist and DC 2001.8 under linux.
In the netlist, there are a few verilog statements with the keywords pullup and pulldown ( i,e, pullup (zero) ).
So, my DC cannot read in this. "pullup not supported by synthesis" or "error at or near token pullup" ( only one instantiated module with the name pullup. i.e
ASIC Design Methodologies and Tools (Digital) :: 06-14-2002 07:00 :: Froed :: Replies: 4 :: Views: 4572
hi,anybody knows how to open the switch of macro defination in ise4.x/5.x
series software,i use xst to synthesis the verilog code,because my codes have
some ifdef...else ...endif,but ise seems like not to support this kind of defination?is it right?any solutions？thanks
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-10-2003 02:46 :: fighter :: Replies: 0 :: Views: 1557
what option/switch must be turned on/off to sign-off asic if use
verilog-xl and nc-verilog?
ASIC Design Methodologies and Tools (Digital) :: 06-12-2003 08:08 :: DeepIC :: Replies: 0 :: Views: 979
run ncsim with -compatibility switch. if it works, then it is like joe2moon said.
ASIC Design Methodologies and Tools (Digital) :: 12-21-2003 18:05 :: rakko :: Replies: 8 :: Views: 2345
Who can recommendate best SW for ATM-switch simulation (Internal Structure)
Software Links :: 11-02-2003 05:05 :: talap :: Replies: 6 :: Views: 902
Good time to switch to VHDL and use the generate statement.
Just kidding, so no flames or starting of a religious war between VHDL and verilog, okay?
I think what a lot of folks do is run a pre-processor, like a perl script, on their verilog code to handle things like this. I mainly use VHDL but I worked at a verilog (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-24-2004 18:25 :: radix :: Replies: 4 :: Views: 1965
The problem was solved fortunatly. Error - wrong switch in my script was the main problem. :?
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-05-2004 03:00 :: Bartart :: Replies: 2 :: Views: 858
I would like your help in a problem that troubles me a lot.
I am using Cadence ICFB 184.108.40.206 with technology files of TSMC_0.13
I have sucesfully run Synopsis and produced a synthesized verilog output.
Then I went to Cadence and imported the verilog file (with reference library TSMC013) and created a schematic view. note th
ASIC Design Methodologies and Tools (Digital) :: 09-29-2004 06:49 :: bigbrother :: Replies: 4 :: Views: 5204
Need VHDL TDM switch example
I find verilog code ( ) , but I`m need VHDL.
Could anybody share this, or TDM switch tutorial
or good Internet resources for this topic, please?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-28-2004 09:03 :: Black Jack :: Replies: 0 :: Views: 1478
anybody tell me how to develop behavior model for switch-cap block? which language and which simulator to use?
Analog Circuit Design :: 04-14-2005 05:12 :: nus_lin :: Replies: 1 :: Views: 674
One side of the switch, if left unconnected can give rise to convergence problems.
Also two nodes that are being inadvertently shorted out can create a problem.
It is difficult to answer without more information. Use a voltage variable resistor as a non-ideal switch and configure very high res for open state and very low res for closed state
Analog Circuit Design :: 05-27-2005 16:39 :: uncle_urfi :: Replies: 9 :: Views: 4809
I wanna write signals to a file using $fdisplay in verilog testbench ,and how can i decide which line to write? that is ,is there any pointer like that in C that I can switch between the lines in the file being writen?
(after each $fdisplay , the file will automatically switch to another line, how can i switch back to (...)
ASIC Design Methodologies and Tools (Digital) :: 06-27-2005 21:39 :: arsenal :: Replies: 1 :: Views: 666
i want to implement an ethernet switch on the fpga
i want to use spartan 3 board
it got 200 000 gate
would that be enough??
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-09-2005 20:02 :: freewilly30 :: Replies: 3 :: Views: 942
verilog is easy to start for hdl.
once u learn u can easily switch to vhdl.
Electronic Elementary Questions :: 08-20-2005 06:34 :: carrot :: Replies: 8 :: Views: 1596
in such case I put bits (for every switchs state)in
a byte and then i use switch-case command.
Electronic Elementary Questions :: 09-13-2005 08:06 :: smxx :: Replies: 2 :: Views: 598
whats the meaning of the switches
access, rc, delay
for the simulator NC verilog
ASIC Design Methodologies and Tools (Digital) :: 12-13-2005 09:58 :: pavanP :: Replies: 3 :: Views: 1433
if my verilog code contains
which from the documentation said it will reset to the default compiler directive value of vcs
What is default value for VCS? where can i get the default value?
`uselib (without any arguments)
what does it do? Does it swith off the previous `uselib in your design? What does it mean by switch off?
ASIC Design Methodologies and Tools (Digital) :: 03-20-2006 22:05 :: yuenkit :: Replies: 1 :: Views: 1064
You already know VHDL so it'll be so simple to start in verilog, since it's much easier than VHDL. verilog is similar to C, so if you have a background on C then life would be rose :D. Some of the "features" of VHDL are dropped out in verilog, and that's what makes verilog much simpler! There are tons of books here in the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-25-2007 05:21 :: salma ali bakr :: Replies: 3 :: Views: 1112
Hello everyone. I am trying to cause an LED to have a delayed (1 second delay) on / off response to a switch which is being toggled. How do I go about creating this delay using VHDL? I am currently using the Spartan3a development board.
I was thinking of using a 'for loop' to cause the delay, but I am not sure if this is the proper or best wa
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-20-2008 13:37 :: Peter_L :: Replies: 5 :: Views: 2156
i have a doubt realted to switch level modeling in verilog.
can the switches called nmos pmos, cmos, tran, tranif0, tranif1 be also used for analog signals.i mean can we give an analog input at the source or drain of these switches and expect an output depending on the control signal which is a digital signal. (...)
Analog Circuit Design :: 03-09-2008 09:11 :: hacksgen :: Replies: 0 :: Views: 520
the program i write is
//cmos inverter switch network
module invert(out, in);
pmos p1 (out, vdd, input);
nmos n1 (out, gnd, input);
and the errors
Line 19: ERROR, syntax error near 'pmos p1 (out, vdd, input)'.
Line 20: ERROR, syntax error near 'nmos n1 (out,
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-25-2008 04:25 :: mr_byte31 :: Replies: 4 :: Views: 691
I was wondering if there was a way to model a floating node in verilog-a. I was actually working on a simple model for a switch (including its on-resistance). What is wish to do is to 'float' the output node when the switch is off...
Analog Circuit Design :: 07-01-2008 11:30 :: bajji_boy :: Replies: 2 :: Views: 1989
modelsim does support systemverilog, try to use the switch "sv" along with vlog to compile systemverilog files.
e.g : vlog -sv
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-01-2008 04:58 :: sree205 :: Replies: 4 :: Views: 958
Hi, I need help designing a circuit with verilog to output a picture onto the screen. I know how to do this with one picture, but I don't know how to do it with multiple pictures.
The objective is to show a picture at a time, which is switched according to user input.
I think I could do the FSM but I'm getting frustrated since I cannot use ou
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-17-2008 13:58 :: alin9980 :: Replies: 2 :: Views: 2681
There is something wrong with the spectre5141.
After switch to spectre5033, the problem disappears.
Analog IC Design and Layout :: 02-16-2009 20:56 :: walkingsun :: Replies: 3 :: Views: 1048
I am trying to simulate a 10 bit 80Ms/s pipeline adc using verilog A models for switch and amplifier, but when i extract the output codes and plot fft i get only around 30 dB. The output codes are fine as i checked them using a ramp test and have no missing codes.
I have tried this for different input frequencies and different sampling
Analog IC Design and Layout :: 05-01-2009 05:43 :: steadymind :: Replies: 3 :: Views: 3055
Check out for SV and vmm complete simple switch example.
If you are interested in developing a environemt for any other protocol, Go to and verify any rtl. If you found any buy in the rtl, send the bug details to .
ASIC Design Methodologies and Tools (Digital) :: 07-27-2009 09:37 :: www.testbench.in :: Replies: 3 :: Views: 2980
You have to interface multiple ethernet PHYs with your FPGA, you have to define the intended switch operation
(switching on which ethernet layer), you can possibly reuse existing ethernet MAC (and if applicable, IP layer) designs
and add the switching logic.
can you provide me some details of design like what are th
Professional Hardware and Electronics Design :: 11-06-2011 14:43 :: mainak001 :: Replies: 5 :: Views: 3467
For starters, add "veriloga" to both your switch-view and stop-view list.
If you find you need to assert netlisting targets on master-
by-master basis, you may have to create a config view
with the Hierarchy Editor to get that control. Otherwise
the switch-view priority will be in the order that the view types
appear in those lists (...)
Analog Circuit Design :: 02-06-2010 16:56 :: dick_freebird :: Replies: 1 :: Views: 1348
How to scan the rotary switch using verilog. I'm new to verilog and FPGA, I've to look for the rotary switch movement and have to increment the data. when i turn the rotary switch it makes FPGA pins to get contact with GND. So in the user guide it has mentioned that we need to pullup the FPGA pin (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-05-2010 07:10 :: Prasanna hegde :: Replies: 0 :: Views: 988
I want to implement an ideal switch using veriloga code.
Can any one help me out with this issue.
Thanks in Advance,
Analog IC Design and Layout :: 06-25-2010 16:30 :: urn :: Replies: 2 :: Views: 3172
you have used system verilog syntax in your code. either you need to remove that key word or use -sv switch to proceed.
ASIC Design Methodologies and Tools (Digital) :: 08-29-2010 12:04 :: santhosh007 :: Replies: 1 :: Views: 758
Not sure about the exact syntax for NCverilog. In ModelSim the switch to be included at command line goes like this:
There should be a similar switch for NCverilog, if not the same one.
You will have to use:
In every file you use those constants.
ASIC Design Methodologies and Tools (Digital) :: 04-30-2011 01:20 :: kulkarni_saurabh :: Replies: 2 :: Views: 1669
Hi, I am using verilog-A to generate a three terminal(3 nodes) switch in CADENCE. My verilog-A file generates the correct IV characteristics that I expect, but when I try to simulate the fan-out(FO) of a device, I realized that Cadence does not capture defined gate capacitance value in verilog-A. In order to capture the (...)
Analog Circuit Design :: 05-13-2011 14:39 :: unluerdincer :: Replies: 2 :: Views: 603
Hi everybody, I am doing my final year project using switch on de2 board to display VGA, code verilog, can u help me!
Hobby Circuits and Small Projects Problems :: 05-16-2011 15:07 :: lamvigian :: Replies: 0 :: Views: 1300
with respect to vcs:
provide the switch : +libext+.vp in the vcs compilation command; rest the vcs tool will take care of it.
ASIC Design Methodologies and Tools (Digital) :: 06-10-2013 06:19 :: pravij :: Replies: 1 :: Views: 2302
Hi, how can I write a verilog code for hexadecimal counter in a way that I program it on the board and change dip switch value ,so I can change the speed of counting?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-23-2011 14:10 :: hodagh :: Replies: 0 :: Views: 645
upf (or cpf) is only here to define voltage island, isolation to add automatically bye the tool the required isolation cell, level shifter, power switch.
the power optimisation, could include gated clock insertion using HVT cells.
The power reduction imply, to have done first the architecture analyzis, before to be on the tool.
ASIC Design Methodologies and Tools (Digital) :: 02-17-2012 03:23 :: rca :: Replies: 10 :: Views: 1795
entity PowerControl is
Clk : in std_logic;
Reset : in std_logic;
ms : in std_logic
-- xbus_hw_idct enable bit
pse_m : out std_logic);
--IDCT switch and isolation control power shut off
architecture rtl of PowerControl
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-30-2012 05:21 :: bravo11 :: Replies: 5 :: Views: 589
You can if you are using Systemverilog; an input or output port can be a variable of any type. Most simulators will support this if you give the file a extension or use a switch to indicate the code is Systemverilog, not plain verilog.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-26-2012 01:36 :: dave_59 :: Replies: 3 :: Views: 1594
we have developed an DES algorithm in verilog.Now i have to implement in FPGA board.Now i have to build a module assigning a switch(north) to the input values that connects to the top module(main module).Please help us with some code.I am new to FPGA
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-06-2012 20:53 :: bhavani403 :: Replies: 1 :: Views: 412
Source and include file paths are only for compilation and have no effect on $fopen.
As an experiment, you could try opening a new file for writing and see where it puts it.
As a lst resort, try giving the full path "C:/Modeltech_pe_edu_10.1d/examples/SystemverilogPractice/switch.txt"
And yes, all versions of ModelSim support (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-20-2013 15:26 :: dave_59 :: Replies: 6 :: Views: 848
please can you help me?
I need switch two SD cards for two MCUs. Only 1 SD to 1 MCU at one time. So I need 2 or 4 pins as selector. Select one of two SD and select one of two processors.
It will be bus selector, or bus switch if you want.
SD card have 6bits of bus. Can I use CPLD for this? Can CPLD drive biderectional? I am totally ne
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-23-2013 18:18 :: darksir :: Replies: 3 :: Views: 307
All tools like cadence incisive, synopsys vcs, mentor graphics modelsim support transistor (switch level primitives) as defined in verilog standard. See those primitives here
ASIC Design Methodologies and Tools (Digital) :: 04-21-2013 20:34 :: tariq786 :: Replies: 6 :: Views: 444
i had done the schematic of a circuit in Dsch3 and generated the verilog code for the same using the option in "make a verilog file". This verilog code is then simulated in Xilinx 12.4. the code has no syntax error and was simulated successfully. but when i need to see the synthesis report it is showing some error like "inv.v" line 25: (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-29-2013 01:13 :: vrunda :: Replies: 0 :: Views: 459
'type' is Systemverilog keyword. Do you use appropriate switch to instruct Conformal that parsed files are SV?
ASIC Design Methodologies and Tools (Digital) :: 05-15-2013 06:39 :: kornukhin :: Replies: 1 :: Views: 644