137 Threads found on edaboard.com: Switch Verilog
I have ap roblem with a entlist and DC 2001.8 under linux.
In the netlist, there are a few verilog statements with the keywords pullup and pulldown ( i,e, pullup (zero) ).
So, my DC cannot read in this. "pullup not supported by synthesis" or "error at or near token pullup" ( only one instantiated module with the name pullup. i.e
ASIC Design Methodologies and Tools (Digital) :: 14.06.2002 07:00 :: Froed :: Replies: 4 :: Views: 4398
hi,anybody knows how to open the switch of macro defination in ise4.x/5.x
series software,i use xst to synthesis the verilog code,because my codes have
some ifdef...else ...endif,but ise seems like not to support this kind of defination?is it right?any solutions？thanks
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.03.2003 02:46 :: fighter :: Replies: 0 :: Views: 1494
what option/switch must be turned on/off to sign-off asic if use
verilog-xl and nc-verilog?
ASIC Design Methodologies and Tools (Digital) :: 12.06.2003 08:08 :: DeepIC :: Replies: 0 :: Views: 927
run ncsim with -compatibility switch. if it works, then it is like joe2moon said.
ASIC Design Methodologies and Tools (Digital) :: 21.12.2003 18:05 :: rakko :: Replies: 8 :: Views: 2238
Who can recommendate best SW for ATM-switch simulation (Internal Structure)
Software Links :: 02.11.2003 05:05 :: talap :: Replies: 6 :: Views: 902
Good time to switch to VHDL and use the generate statement.
Just kidding, so no flames or starting of a religious war between VHDL and verilog, okay?
I think what a lot of folks do is run a pre-processor, like a perl script, on their verilog code to handle things like this. I mainly use VHDL but I worked at a verilog (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.04.2004 18:25 :: radix :: Replies: 4 :: Views: 1830
The problem was solved fortunatly. Error - wrong switch in my script was the main problem. :?
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.06.2004 03:00 :: Bartart :: Replies: 2 :: Views: 740
I would like your help in a problem that troubles me a lot.
I am using Cadence ICFB 126.96.36.199 with technology files of TSMC_0.13
I have sucesfully run Synopsis and produced a synthesized verilog output.
Then I went to Cadence and imported the verilog file (with reference library TSMC013) and created a schematic view. note th
ASIC Design Methodologies and Tools (Digital) :: 29.09.2004 06:49 :: bigbrother :: Replies: 4 :: Views: 4841
Need VHDL TDM switch example
I find verilog code ( ) , but I`m need VHDL.
Could anybody share this, or TDM switch tutorial
or good Internet resources for this topic, please?
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.12.2004 09:03 :: Black Jack :: Replies: 0 :: Views: 1369
anybody tell me how to develop behavior model for switch-cap block? which language and which simulator to use?
Analog Circuit Design :: 14.04.2005 05:12 :: nus_lin :: Replies: 1 :: Views: 637
One side of the switch, if left unconnected can give rise to convergence problems.
Also two nodes that are being inadvertently shorted out can create a problem.
It is difficult to answer without more information. Use a voltage variable resistor as a non-ideal switch and configure very high res for open state and very low res for closed state
Analog Circuit Design :: 27.05.2005 16:39 :: uncle_urfi :: Replies: 9 :: Views: 4609
I wanna write signals to a file using $fdisplay in verilog testbench ,and how can i decide which line to write? that is ,is there any pointer like that in C that I can switch between the lines in the file being writen?
(after each $fdisplay , the file will automatically switch to another line, how can i switch back to (...)
ASIC Design Methodologies and Tools (Digital) :: 27.06.2005 21:39 :: arsenal :: Replies: 1 :: Views: 585
i want to implement an ethernet switch on the fpga
i want to use spartan 3 board
it got 200 000 gate
would that be enough??
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.07.2005 20:02 :: freewilly30 :: Replies: 3 :: Views: 857
verilog is easy to start for hdl.
once u learn u can easily switch to vhdl.
Electronic Elementary Questions :: 20.08.2005 06:34 :: carrot :: Replies: 8 :: Views: 1502
1. Read is easy since it is output from your register. All you need is branch the data out to the data input of your modules.
2. Write need arbitration. You should prioritize your modules, or have a fairness engineer to even the access right for each module. The arbitration logic would switch write access for your module, depends on the rule you
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.08.2005 15:06 :: sinwave :: Replies: 2 :: Views: 707
in such case I put bits (for every switchs state)in
a byte and then i use switch-case command.
Electronic Elementary Questions :: 13.09.2005 08:06 :: smxx :: Replies: 2 :: Views: 543
I have 3 sub-blocks and a top module load them with the conditioanl compilation command, here is parts of the top module.
N45TT N0TT1 (.in(output1), .out(OUTTT1));
N50TT N0TT1 (.in(output1), .out(OUTTT1));
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.09.2005 18:30 :: walkon :: Replies: 3 :: Views: 1793
Perhaps you know this already: ncelab has a -notimingcheck - but that is a global switch - truns off for ALL instances.
If your concern is X-propagation due to timing violation (and not the violation iself), try using no_notifier flag, again global.
For instance specific stuff few ideas:
1. If you like this no_notifier kind of thi
ASIC Design Methodologies and Tools (Digital) :: 09.10.2005 23:00 :: aji_vlsi :: Replies: 6 :: Views: 11365
whats the meaning of the switches
access, rc, delay
for the simulator NC verilog
ASIC Design Methodologies and Tools (Digital) :: 13.12.2005 09:58 :: pavanP :: Replies: 3 :: Views: 1309
A disconnected output also has a voltage value. To see the high-z effect, you should connect another low-z driving source to this node.
Can you advise me how do i code this in verilogA? Thanks :)
Add another module with low Zout. Short the ouput of these two module. If one (and only one in this c
Analog IC Design and Layout :: 20.03.2006 00:21 :: Hughes :: Replies: 6 :: Views: 2142
if my verilog code contains
which from the documentation said it will reset to the default compiler directive value of vcs
What is default value for VCS? where can i get the default value?
`uselib (without any arguments)
what does it do? Does it swith off the previous `uselib in your design? What does it mean by switch off?
ASIC Design Methodologies and Tools (Digital) :: 20.03.2006 22:05 :: yuenkit :: Replies: 1 :: Views: 978
professionally, when it comes to industry, most of the companies use either Emacs or VI .. I have previousely used VI and it is fantastic in editing text .. it gives you almost everything to do whatever you want with text .. the first thing I learnt was to copy a column in the middle of the text file and that made me interested in continuing with V
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.05.2007 03:38 :: omara007 :: Replies: 42 :: Views: 32510
I am woking on 2 bit home security system with following inputs.
2 bit passwords
1 bit from door sensor on and off
1 bit switch monitor or not to monitor
led1 act as alarm when door is opened witout entering correct passwords i.e door sensor is set to 1
led2 will glow after 10 sec timer if correct password has not been e
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.06.2007 05:51 :: BAT_MAN :: Replies: 0 :: Views: 815
Thanks, but the controller does not have the local side data IO. I need the data IO to switch the SDRAM between the two DSPs.
I may need to modify your code. Thankz anyways.
ASIC Design Methodologies and Tools (Digital) :: 20.11.2007 06:38 :: vlsi_whiz :: Replies: 3 :: Views: 6712
You already know VHDL so it'll be so simple to start in verilog, since it's much easier than VHDL. verilog is similar to C, so if you have a background on C then life would be rose :D. Some of the "features" of VHDL are dropped out in verilog, and that's what makes verilog much simpler! There are tons of books here in the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.11.2007 05:21 :: salma ali bakr :: Replies: 3 :: Views: 1034
Hello everyone. I am trying to cause an LED to have a delayed (1 second delay) on / off response to a switch which is being toggled. How do I go about creating this delay using VHDL? I am currently using the Spartan3a development board.
I was thinking of using a 'for loop' to cause the delay, but I am not sure if this is the proper or best wa
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.02.2008 13:37 :: Peter_L :: Replies: 5 :: Views: 1998
i have a doubt realted to switch level modeling in verilog.
can the switches called nmos pmos, cmos, tran, tranif0, tranif1 be also used for analog signals.i mean can we give an analog input at the source or drain of these switches and expect an output depending on the control signal which is a digital signal. (...)
Analog Circuit Design :: 09.03.2008 09:11 :: hacksgen :: Replies: 0 :: Views: 460
the program i write is
//cmos inverter switch network
module invert(out, in);
pmos p1 (out, vdd, input);
nmos n1 (out, gnd, input);
and the errors
Line 19: ERROR, syntax error near 'pmos p1 (out, vdd, input)'.
Line 20: ERROR, syntax error near 'nmos n1 (out,
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.04.2008 04:25 :: mr_byte31 :: Replies: 4 :: Views: 638
I am having code for same in VHDL .Check it out whether it is useful to you or not.
If USEFUL PLEASE PRESS HELP BUTTON.
Code for Hamming Distance Transmission & Reception.
--Program for HAMMING CODE TRANSMISSION & RECEPTION .
-- ( generating Hamming code parellely , ssending it serially &
-- receiving it parallely for error d
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.06.2008 10:04 :: victoria_jitesh :: Replies: 8 :: Views: 7888
I was wondering if there was a way to model a floating node in verilog-a. I was actually working on a simple model for a switch (including its on-resistance). What is wish to do is to 'float' the output node when the switch is off...
Analog Circuit Design :: 01.07.2008 11:30 :: bajji_boy :: Replies: 2 :: Views: 1815
modelsim does support systemverilog, try to use the switch "sv" along with vlog to compile systemverilog files.
e.g : vlog -sv
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.09.2008 04:58 :: sree205 :: Replies: 4 :: Views: 859
Hi, I need help designing a circuit with verilog to output a picture onto the screen. I know how to do this with one picture, but I don't know how to do it with multiple pictures.
The objective is to show a picture at a time, which is switched according to user input.
I think I could do the FSM but I'm getting frustrated since I cannot use ou
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.11.2008 13:58 :: alin9980 :: Replies: 2 :: Views: 2441
There is something wrong with the spectre5141.
After switch to spectre5033, the problem disappears.
Analog IC Design and Layout :: 16.02.2009 20:56 :: walkingsun :: Replies: 3 :: Views: 1004
I am trying to simulate a 10 bit 80Ms/s pipeline adc using verilog A models for switch and amplifier, but when i extract the output codes and plot fft i get only around 30 dB. The output codes are fine as i checked them using a ramp test and have no missing codes.
I have tried this for different input frequencies and different sampling
Analog IC Design and Layout :: 01.05.2009 05:43 :: steadymind :: Replies: 3 :: Views: 2975
Check out for SV and vmm complete simple switch example.
If you are interested in developing a environemt for any other protocol, Go to and verify any rtl. If you found any buy in the rtl, send the bug details to .
ASIC Design Methodologies and Tools (Digital) :: 27.07.2009 09:37 :: www.testbench.in :: Replies: 3 :: Views: 2837
You have to interface multiple ethernet PHYs with your FPGA, you have to define the intended switch operation
(switching on which ethernet layer), you can possibly reuse existing ethernet MAC (and if applicable, IP layer) designs
and add the switching logic.
can you provide me some details of design like what are th
Professional Hardware and Electronics Design :: 06.11.2011 14:43 :: mainak001 :: Replies: 5 :: Views: 3258
For starters, add "veriloga" to both your switch-view and stop-view list.
If you find you need to assert netlisting targets on master-
by-master basis, you may have to create a config view
with the Hierarchy Editor to get that control. Otherwise
the switch-view priority will be in the order that the view types
appear in those lists (...)
Analog Circuit Design :: 06.02.2010 16:56 :: dick_freebird :: Replies: 1 :: Views: 1261
I am trying to make a PWM to the specifications in the attached word document. I get no errors or warnings in my my synthesis or implementation, but the design does not work. When my program/enable switch is high, pressing the buttons does not increment or decrement.
The word document is located in the zip file and is called Lab4.doc.
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.02.2010 01:42 :: Aurixious :: Replies: 1 :: Views: 1257
How to scan the rotary switch using verilog. I'm new to verilog and FPGA, I've to look for the rotary switch movement and have to increment the data. when i turn the rotary switch it makes FPGA pins to get contact with GND. So in the user guide it has mentioned that we need to pullup the FPGA pin (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.03.2010 07:10 :: Prasanna hegde :: Replies: 0 :: Views: 910
can you correct my code... i dont how to use switch with the clock. so that when i on the swicth the clock start j is start counting. plez help me.
output reg keluar,
// reg result = 6'b000000;
reg en = 1'b0;
reg i = 0;
integer j= 0;
always @ ( posedge clk)
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.03.2010 05:19 :: alierossi :: Replies: 3 :: Views: 989
I want to implement an ideal switch using veriloga code.
Can any one help me out with this issue.
Thanks in Advance,
Analog IC Design and Layout :: 25.06.2010 16:30 :: urn :: Replies: 2 :: Views: 2742
I have a top level verilog file, which declares all the inputs, outputs, regs and wires for several sub-files.
FetchStage1 fs1( .stall_i(instBufferFull | ctiQueueFull),
I get the following error while compiling:dot name: Use -sv switch to enabl
ASIC Design Methodologies and Tools (Digital) :: 02.08.2010 14:34 :: Manwe :: Replies: 1 :: Views: 629
I have written a code which i have implemented in Spatran 3E kit. The program glows the LEDs of kit in sequenceform when i select the DIP switch. I mean first of all, first LED glows, then first two ,then first three and so on.
What all i want is that when i select second DIP switch, what so ever numbering is going to Diaplay LED, it should Halt a
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.12.2010 14:45 :: moonnightingale :: Replies: 1 :: Views: 590
maybe, it is not work because of the 'debounce' switch..hehe
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.03.2011 00:25 :: zel :: Replies: 12 :: Views: 2366
Not sure about the exact syntax for NCverilog. In ModelSim the switch to be included at command line goes like this:
There should be a similar switch for NCverilog, if not the same one.
You will have to use:
In every file you use those constants.
ASIC Design Methodologies and Tools (Digital) :: 30.04.2011 01:20 :: kulkarni_saurabh :: Replies: 2 :: Views: 1333
Hi, I am using verilog-A to generate a three terminal(3 nodes) switch in CADENCE. My verilog-A file generates the correct IV characteristics that I expect, but when I try to simulate the fan-out(FO) of a device, I realized that Cadence does not capture defined gate capacitance value in verilog-A. In order to capture the (...)
Analog Circuit Design :: 13.05.2011 14:39 :: unluerdincer :: Replies: 2 :: Views: 546
Hi everybody, I am doing my final year project using switch on de2 board to display VGA, code verilog, can u help me!
Hobby Circuits and Small Projects Problems :: 16.05.2011 15:07 :: lamvigian :: Replies: 0 :: Views: 1209
check "ram_style" switch in XST, you can use "-ram_style distributed" if you don't want memory to be inferred as Block RAM
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.08.2011 09:17 :: dcreddy1980 :: Replies: 11 :: Views: 2022
with respect to vcs:
provide the switch : +libext+.vp in the vcs compilation command; rest the vcs tool will take care of it.
ASIC Design Methodologies and Tools (Digital) :: 10.06.2013 06:19 :: pravij :: Replies: 1 :: Views: 1836
Hi,I need a verilog code for a banyan switch...
if there are two inputs say x1 and x2
and two outputs say y1 and y2
there is a select line s
for s=0 i must send the data through upper port
for s=1 i must send data through lower port.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.11.2011 13:58 :: prasan61 :: Replies: 2 :: Views: 1274