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81 Threads found on Switch Verilog
You can not ! as I know if you want to produce pulse train you can use a pulse source in series with an ideal switch and contolr the switch with another pulse source
If I still remember, in irun, you explicitly specify the TOP module name using the -top switch. There are separate switches to specify verilog and VHDL files, use them. These are trivial errors and can be easily solved by reading the user guide.
When closing/breaking an electrical circuit via mechanical means - I.E: a push button, a switch, etc... The operation will usually multiple toggles. This is because of the "imperfect nature" of the contacts.
First of all buttons will have contacts that bounce when being closed and many times when being opened too. You need to debounce your select input. You need to make sure the value you are waiting for is there for at least 10-20 ms before generating a debounced output (db_select) that indicates the switch has changed to a new level. This will give
Hi Guys. I wanted to use the DE1 D5M camera module and when I capture the image and let's say switch on SW, the image will be converted to a grayscale image and output it through VGA in a monitor. How can I do this in verilog? Please help me?
The one with the lower impedance will win as it is used as a switch.
irun uses the file extension to determine what language you want the file compiled as: verilog, Systemverilog, VHDL or SystemC. So as far as I can understand, your m_def.h is not being recognized by irun. 1> Try changing the file extension of m_def.h to any of the standard know types. 2> Try using the irun switch -vlog_ext keeping m_def.h (...)
Hi, I am designing a hybrid content addressable memory (CAM) using cadence and I need to build a verilog-A block to switch modes. In the read mode, I need to pre-charge some nodes then make them floating. I tried different verilog-a lines but the code always fails. For example, I tried using the following line that I found while (...)
To support Systemverilog, most tools require that your files have a file extension. They may also have a global switch (ModelSim has -sv) that makes it treat all verilog files as Systemverilog, but I strongly recommend not using that switch as some legacy verilog files will not compile in (...)
Hello, Ill try to answer a question as I seem to only leech off the boards :D so forgive me if this isn't that helpful. I'm not that well versed in verilog, I've mostly used VHDL but this might help you. 1) yes you are quite right you will need some denouncing for your switch these are common and you can find some code for it online. 2) have a po
Hello Everyone, I am new to the verilog-A programming. I have a model for MOSFET switch written in verilog-a. Now I want to construct inverter by instantiating the mosfet model. How do I do this. Is the instantiating method same as the method used in verilog. Ex: mosfet mosfet_1(D G S B); Please help me. Thank You
Hello Experts, I am new to use of verilog-A programming. I had question regarding the use of this language. I want to design the NEMS switch model using the verilog-A model. Once I design this model will I be able to create a circuit simulation model of the NEMS switch which can be used as a model in PSPICE netlist to (...)
I've tried this and found the created schematic a nearly useless, unreadable mess. Now, I do not see verilog (different than veriloga) in your view-list. But an analog simulator is not going to switch into digital views usefully anyway. The mixed signal setup involves partitioning and somebody somewhere has to insert all of the (...)
You should not need a -sv switch if your files already have a extension. If fact, I would discourage using it so that legacy verilog .v files don't have problems when they have used Systemverilog keywords as identifiers. Try vlog
I need a verilog code for switch with 50 inputs,12 outputs and 12 select lines. Both the inputs and outputs are 256 bit wide. in select lines i need to mention the which 12 inputs should appear at the output. For ex. if I need the inputs 2,5,9,14,20,25,27,32,36,40,44,49 to appear in the output i should give these numbers in select lines. Kindly not
Why do you want it to use a switch statement? Wait, don't tell me ... your assignment says you have to use a switch statement. For educational purposes. Well, that settles it then. You can figure it out in an effort to actually learn something. Enjoy your education! :) If you want help, you'll have to come up with some specific problem. Not ...
If you have a recent version of ModelSim, you can dovlog hello.c vsim -c hello -do "run -all;quit"This automatically compiles your DPI C code and creates a shared library that is automatically loaded by vsim. A couple of other notes: We do not recommend using the vlog -sv switch. This will treat any verilog *.v file a
Hi, How can I use the command line option as a switch inside verilog model ? Ex: My command line is (say) ncelab -delay_mode unit (or) ncelab -delay_mode zero How can I use "unit" or "zero" inside verilog model ? Requirement is: I want to change some timings depends on this switch. Regards, suresh
The file is created by vlog if you use it to compile your C files, and then loaded automatically by vsim. BTW, you should not use the -sv switch. Instead, use for Systemverilog files and keep *.v for verilog-only files.
'type' is Systemverilog keyword. Do you use appropriate switch to instruct Conformal that parsed files are SV?
If you can use Systemverilog, this is quite easy because testbenches are written using dynamically constructed classes and you can read command line switches to help you select which classes to construct. The object-oriented nature of classes makes it possible to switch one class for another at many different levels of the testbench without (...)
hi., i had done the schematic of a circuit in Dsch3 and generated the verilog code for the same using the option in "make a verilog file". This verilog code is then simulated in Xilinx 12.4. the code has no syntax error and was simulated successfully. but when i need to see the synthesis report it is showing some error like "inv.v" line 25: (...)
All tools like cadence incisive, synopsys vcs, mentor graphics modelsim support transistor (switch level primitives) as defined in verilog standard. See those primitives here
Hello, I am having the following error while trying to compile my SV codes. I'm getting this error for my verification codes. Error- Syntax error Following verilog source has syntax error : Class declaration outside programs requires "-sverilog -ntb_opts dtm" switch "../verification/", 4: token is ';' cl
Hi boys, please can you help me? I need switch two SD cards for two MCUs. Only 1 SD to 1 MCU at one time. So I need 2 or 4 pins as selector. Select one of two SD and select one of two processors. It will be bus selector, or bus switch if you want. SD card have 6bits of bus. Can I use CPLD for this? Can CPLD drive biderectional? I am totally ne
why dont you switch to verilog instead of system verilog and then try to compile. I dont see any advantage using system verilog to test an adder.
at first change output leds to output reg leds and comment out 'reg leds'; then read carefully compilation warnings; check what leds signal level, 'LOW' or "HIGH', switch your board LEDs 'ON'; j.a
Hi. I want to design a verilog-a model of a two way switch. You can see the code below. When I run the simulation the "FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit..." error pops up. Searching on the internet I found something about switching branches in verilog-a which might (...)
we have developed an DES algorithm in verilog.Now i have to implement in FPGA board.Now i have to build a module assigning a switch(north) to the input values that connects to the top module(main module).Please help us with some code.I am new to FPGA
Couple suggestions: 1. Check Environment (Setup/Environment/switch View List). Must contain "veriloga" 2. Use resistor models from built in libraries: ahdlLib (veriloga model); and analogLib (spice model). See if you are able to probe currents/voltages/dc operating points. If the result is still negative: check your library version with (...)
Hi, im new in verilog coding, i need help for the 2-line LCD display in Altera DE2 board I want to write a coding when switch 1 on, it will change the text in display and address value, and for the switch 2 I have compiled the coding and found some error, so someone help me solve the problem? always @(posedge CLOCK_50 or negedge SW)
I have an issue with trying to figure out how to implement a simple switch (as in OPEN or CLOSE circuit) in verilog. Some background: I have a device that takes user button presses (mostly a capacitive switch) and I have a design that will automatically "press buttons" given certain conditions. The plan I have is to make a small module (...)
hi frnds, how NoC switch and its links can be modeled in gate-level using verilog hdl. if anyone has knwledge about this topic plz reply.. Thanks
It's just a look-up table... use a switch statement
Hi, how can I write a verilog code for hexadecimal counter in a way that I program it on the board and change dip switch value ,so I can change the speed of counting?
I would build a separate testbench for this AC analysis. Just the switch-able capacitor and a (perhaps verilog-a) control block that selects them. If you do not like the previous solution, you could also write an ocean script and go thru all the codes.
Hi,I need a verilog code for a banyan switch... if there are two inputs say x1 and x2 and two outputs say y1 and y2 there is a select line s for s=0 i must send the data through upper port for s=1 i must send data through lower port.
Is there any particular switch available in ModelSim Simulator where I can add "one delay unit" and compile my design?
with respect to vcs: provide the switch : +libext+.vp in the vcs compilation command; rest the vcs tool will take care of it.
I compiled your code with quartus with such for loops: output /*wire*/ reg r_data /...../ integer i; always @(posedge clk) if (wr_en) for (i = 0; i < CHNK_FACT; i = i + 1) array_reg <= w_data; /....../ always @*
Hi everybody, I am doing my final year project using switch on de2 board to display VGA, code verilog, can u help me! Thanks regards
Hi, I am using verilog-A to generate a three terminal(3 nodes) switch in CADENCE. My verilog-A file generates the correct IV characteristics that I expect, but when I try to simulate the fan-out(FO) of a device, I realized that Cadence does not capture defined gate capacitance value in verilog-A. In order to capture the (...)
Not sure about the exact syntax for NCverilog. In ModelSim the switch to be included at command line goes like this: +incdir+directory_for_include_files There should be a similar switch for NCverilog, if not the same one. You will have to use: `include "my_include_file.v" In every file you use those constants.
i am newbie in verilog and just dont know what is wrong with my code. this is the crazy simple question: Develop a verilog model for a thermostat that has two 8-bit unsigned binary inputs representing the target temperature and the actual temperature in degrees Fahrenheit (˚F). Assume that both temperatures are above freezing (32˚F).
maybe, it is not work because of the 'debounce' switch..hehe
Hello i want to make a radio control car for my son and i need some PWM verilog code or example for spartan 3E i wantto control 4 DC motors and all of them to move formward or backword by a switch from spartan 3e pls help
I have written a code which i have implemented in Spatran 3E kit. The program glows the LEDs of kit in sequenceform when i select the DIP switch. I mean first of all, first LED glows, then first two ,then first three and so on. What all i want is that when i select second DIP switch, what so ever numbering is going to Diaplay LED, it should Halt a
I have a top level verilog file, which declares all the inputs, outputs, regs and wires for several sub-files. FetchStage1 fs1( .stall_i(instBufferFull | ctiQueueFull), .clk(clock), .reset(reset), .lastPC) I get the following error while compiling:dot name: Use -sv switch to enabl e
can you correct my code... i dont how to use switch with the clock. so that when i on the swicth the clock start j is start counting. plez help me. module counter( output reg keluar, input clk, input switch, ); // reg result = 6'b000000; reg en = 1'b0; reg i = 0; integer j= 0; always @ ( posedge clk) begin
Hi, How to scan the rotary switch using verilog. I'm new to verilog and FPGA, I've to look for the rotary switch movement and have to increment the data. when i turn the rotary switch it makes FPGA pins to get contact with GND. So in the user guide it has mentioned that we need to pullup the FPGA pin (...)