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21 Threads found on edaboard.com: Symmetric Load
No problem. Just asymmetrically loaded power grid.
Both BJT or CMOS, the Class-A Power Amplifiers are always biased for symmetric swing around the that OP is selected in according with load Line theory.
Hello, I am designing a basic Maneatis cell and I am trying to size the symmetric load so that one pmos works in linear and the other in saturation, as it is diode connected. My Vdd=1V and the output DC level should be 0.5V, which means that Vds across both pmos transistors should be 0.5V. This value is suitable for the diode connected, but in c
Hi, Implementing a non overlapping clock generator (NOCG) is fairly straightforward. But my problem is that the generated non-overlapped clocks are not symmetric (On time of the two non-overlapped clocks is slightly different). I read somewhere that adding an asymmetric transmission gate will help having symmetric clocks, but I could not (...)
hi I want to calculate delay time for this cell with analytic equation and software, but I don't know how I do this I would be glad if anyone help me to do this
Hi All, I just want to know about symmetric load, how it works. Why it is termed as a symmetric load , even it's not at all symmetric across its voltage swing. and it's not even acting as a linear resistor. but people are reporting this as a resistor which can acts as a variable resistor for voltage (...)
Hello, Would I be able to get your thoughts on the following design? I have a load (piezo , active load 50Ohm) that I would like to send it a single symmetric narrow pulse (pulse duration 20ns - 100ns) with Peak-to-Peak (0 ... 140V). I have designed the switching circuitry to pulse this thing for adjustable amount of time. However, I (...)
No L293 doesn't need dual supply (symmetric). What are the specs of your motor? If it can turn without load but stops with load then the power is not good enough of the current that L293 provides is not enough. Alex
Dear all, I have designed fully differential symmetric SC-amplifier. When i load differential output with equal capacitive load (say, C1), then differential output is, say, y. But when i load differential output with unequal capacitive load (C1,C2), then differential output is y?Δ for the same input (...)
Hello friends, I have one question about Maneatis's paper "Low-jitter and process-independent DLL and PLL based on self-biased techniques". This paper use a diode-connected symmetric load to building the resistor in LPF, using the replica baising circurt I think the resistor is in Vctrl buffer. My question is where is the voltage source ?
Hi all, Can any one help me to know what is the purpose of using a symmetric load in a differential ring VCO..?
Hai.... Why we are using same size transistor in symmetric load ? If we choose different size means what will happen?
Use the attached schematic, gain is (R2/R3)+1 in my schematic it is (9/1)+1=10 R1 is just in input load resistor, you can remove it if it not needed. 52316 CORRECTION this works for DC pulses, if you have actual AC you need to use symmetric power supply, or a bias in the input. Are you sure that the signal you hav
Hi Guys, I am simulating a VCO with the following design: Process: 0.18 um Tool: Cadence Spectre Topology:Three stage Differential amplifier (with symmetric load) Supply: 3.3V Frequency: 2.4GHz I measured the phase noise and it was -100 dbc/Hz at 10 MHz. Is this a good performance? I am using a DC control voltage of about 875 mV. How
Good evening to all friends! build the source that attached only changing the frequency of operation to 55kHz, the input voltage is 110v and the voltage output is now 50VDC symmetric. my project is to 9A 50VDC and-50VDC-9A. My problem is with load connected between the + and - isolating the source of land output (100VDC) and a load of (...)
The VCO i used is popular Maneatis delay cell (symmetric load consist of a diode-connected PMOS device in shunt with an equally sized biased PMOS device). As i know, input voltage is higher, while the out frequency is higher. but why my tuning curve is not normal? I am confused. why??? plz help me!
1. A differential VCO doubles the signal swing thereby increasing the carrier power. So Phase noise improves. Moreover the substrate noise gets canceled within the VCO., does not introduce current spikes on the supply line, low harmonics and lower supply pushing. 2. The load that the VCO sees must be symmetric as well., or else the imbalance will
Mostly the systematic offset comes at the stage where you convert from symmetric to asymmetric. Design the VDSAT of the active loads equal to the VDSAT of the output stage active device. The you get a balanced active load voltage. Did not try to make it extreme balanced. Mismatches are already imbalance.
(Referring to the PDF attachment) In the symmetric load of the VCDL, a diode connected PMOS and a PMOS of same size are connected in parallel. The gate of the other PMOS is connected to the control voltage. It is said that the by varying the control voltage the resistance of the symmetric load is varied and the delay of (...)
Ropt=2*(Vcc-Vsat)/Ic(max) if Vcc=2.7V , Idc=1mA so Imax=2mA (two times of Idc for symmetric operation) and we assume Vsat=0.25V Ropt=2*(2.7-0.25)/2E-3=2450 Ohm. With this Ropt you'll find 1.225mW output power that is not "really" power amplifier.. load Line theory is only used to predict "range of load other hand, there are
Hi, I am designing a differential ring oscillator using 0.13 technology. I used four Maneatis symmetric load delay cells. I can get it oscillate ( around 2-4GHz). But the phase noise is always very large (around -60dBc/Hz at 1MHz offset). Thank you.