15 Threads found on edaboard.com: Synopsys 2008
I run Hspice from matlab. I have a program for optimization where I need to run Hspice many times consecutively. After every simulation the pop up window appears
And i need to hide the popup windows because that makes the program run slower I read a post that says just putting /min
system('C:\synopsys\Hspice_A-2008.03\BIN\hspice -i C:\cascode\cmo
Software Problems, Hints and Reviews :: 04-11-2016 15:12 :: isaac14 :: Replies: 1 :: Views: 525
O.K., HREAD (=hexread) is a function from stdlogic_texio, a non-standard synopsys library.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-17-2016 11:46 :: FvM :: Replies: 5 :: Views: 776
I am having problems with synopsys Design Compiler (version 2007-03-sp1) and VHDL fixed-point library. I have mapped to lib ieee_proposed the files fixed_float_types_c.vhdl and fixed_pkg_c.vhdl taken from the archive "synopsys.zip" on the "VHDL-2008 Support Library web page".
I am getting error when I analyze the file (...)
ASIC Design Methodologies and Tools (Digital) :: 11-12-2013 10:14 :: DVB_master :: Replies: 2 :: Views: 1238
we have an FPGA project with a synopsys dc_shell - Xilinx ISE
design flow. There are dc_shell scripts that used to work well, but now
the command syntax has obviously changed to TCL in version B-2008.09.
That is not a problem.
But, when I try to do
write -f edif
I get the error message:
Error: format EDIF not suppor
ASIC Design Methodologies and Tools (Digital) :: 05-19-2012 09:14 :: sp_sara :: Replies: 0 :: Views: 1437
or_reduce() is from synopsys "IEEE".std_logic_misc. It's a reduction or function, ORing all bits of a bit vector.
In VHDL 2008, the reduction operation is achieved with an extended syntax
std_logic_var <= OR std_logic_vector_var
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-16-2012 20:34 :: FvM :: Replies: 19 :: Views: 910
I am using synopsys Design Compiler (Version B-2008.09) to create a Verilog file from a circuit specified in several VHDL files.
The top level circuit given in VHDL includes several shift registers:
entity cossma is
input: in std_logic_vector(3 downto 0);
clk: in std_logic;
set_ff: in std_logic;
set_ff_data : in
ASIC Design Methodologies and Tools (Digital) :: 10-07-2011 11:52 :: Ludwick :: Replies: 2 :: Views: 909
I got error when I run DFT 2008.9. The command "insert_dft" responds "Invalid test protocol". The old command "inser_scan" is supported.
Run "set_dft_signal" responds "-type not found". What type should I set?
As I know, the Test_Compiler "set_scan_signal" type is "test_scan_enable".
Why it is wrond on DFT_COmpiler?:-(:-(
ASIC Design Methodologies and Tools (Digital) :: 11-16-2010 08:58 :: charles_hoho :: Replies: 9 :: Views: 4374
At the moment my standard synthesis script for Design Compiler is something like:
set target_library "/opt/.../synopsys/synthesis/2008.09-SP3/libraries/syn/and_or.db"
set link_library "* /opt/.../synopsys/synthesis/2008.09-SP3/libraries/syn/and_or.db"
define_design_lib WORK -path ./WORK
analyze -format vhdl (...)
ASIC Design Methodologies and Tools (Digital) :: 02-23-2010 22:32 :: ESD_UNIVR :: Replies: 0 :: Views: 1189
I use AMBA APB to configure a dut with systemverilog, the APB I used is synopsys vip. the attachment is the code.
when run it failed as: (vcs use 2008.06 )
Error- Package not defined
Package scope resolution failed. Token 'ApbMaster_rvm' is not a package.
ASIC Design Methodologies and Tools (Digital) :: 01-29-2010 07:39 :: helen_yuqm :: Replies: 0 :: Views: 2916
Can i use mentor ic station 2008 for place and routing along eith design analyzer of synopsys?
Elementary Electronic Questions :: 09-16-2009 12:30 :: iannisk :: Replies: 1 :: Views: 809
I am using synopsys 2008.09 Design Compiler and IC Compiler, I want to convert "lef" files to "plib" files and eventually to "pdb" library files. In synopsys Physical Compiler the "lef2plib" command does this, but I don't have Physical compiler.
What can I do? Would you please help me ?
ASIC Design Methodologies and Tools (Digital) :: 08-21-2009 12:02 :: massdood :: Replies: 2 :: Views: 2082
I was trying to run synopsys Hercule DRC using Hercule VUE (graphical interface) but I encountered a strange error. Here is the complete error log. The error is near the end of the log.
Hercules (R) Hierarchical Design Verification, SUN.64 Release B-2008.09.18103 2008/08/21
(C) Copyright 1996, 1997, 1998, 1999, 2000, 2001
Analog Circuit Design :: 05-20-2009 07:11 :: pokemonstation :: Replies: 0 :: Views: 1727
I think that is the same problem I had once ... took me a good while to figure this one out.
Go to /home/synopsys/2008.3/hspice/
you should see something like this there
bin cmi hspice_cmd_help license.warn mosraapi README
cds demo HSPICE.html linux parts
cds.tar docs hspice.ini meta.cfg
Software Problems, Hints and Reviews :: 03-21-2009 00:09 :: R00KIE :: Replies: 3 :: Views: 4820
Hi all , forum helped me a lot ,
however i still have a problem this time with Hercules:
I use Cosmos as layout tool with his default demo lib.
When i tryed to check any cell for DRC an error happens
Hercules (R) Hierarchical Design Verification, IA.32 Release B-2008.09.18103 2008/08/21
(C) Copyright 1996, 1997, 1998, 1999,
Linux Software :: 03-04-2009 20:26 :: MechaniX :: Replies: 2 :: Views: 2917
hspice_vB-2008.09 has already been available for over one month.
It was released on synopsys's ftp on 09/04/2008.
Software Problems, Hints and Reviews :: 10-24-2008 20:44 :: tsinghua :: Replies: 1 :: Views: 1092