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22 Threads found on edaboard.com: Synopsys And Tcl
To accelerate design, I used following commands for multiple CPU processing command in Cadence Encounter APR tcl file: " setMultiCpuUsage -acquireLicense 8 -localCpu max" It seems working fine. For Cadence Virtuoso Calibre DRC/LVS, may I use similar tricks to make it run faster? It's pretty slow for a large design. Also, is (...)
hi, well after fixing some issues with libraries and everything else, now I encounter another error while running synopsys primepower which says : can't open init file .pt_procs.tbc before this, I was getting the following error: can't open pt_procs.tcl so I've found another one in the primetime directory and I (...)
Hi everyone, I am using Faraday-90nm library. My lib_search path for tcl file is /Cadence/libraries/Faraday-90nm-Faraday90nm-SP/Design-Kits/2010/fs0a_a//2010Q4v2.1/GENERIC_CORE/FrontEnd/synopsys/synthesis and the target library is fs0a_a/generic_core_ff1p32vm40c.lib. The verilog file is a accu.v (accumulator). I am using the gui (...)
I need some synopsys tetramax help. I have generated compressed and uncompressed serial patterns for a chain test. At the end of of tcl, I wrote the patterns as: write_patterns -format STIL -ser -first 0 -last 0 While the the uncompressed generates pattern0 with load and unload, the compressed generates 2 pattersn (...)
Hi, I'm using the PT(PrimeTime) and ICC(IC Compiler) of synopsys for timing closure. The "fix_eco_timing" command of PT is very powerful for timing ECO. Timing ECO script(tcl) which is generated from "fix_eco_timing/write_changes" command of PT is used for timing ECO in ICC. But this ECO script is for (...)
A design has an address bus 32 bits wide of which only 2 bits go into a module. You create an extra level of hierarchy in DC using the group command and only 2 bits of the address needed go into the newly created module. DC brings in all 32 bits into the module and does not connect the top 30. Is there a way to get rid f the unused bus (...)
Hi All; I am trying to optimize my design using Power Compiler (synopsys) and looking for Power Compiler' Usermanual and Tutorials. It seems to be not available in this forum and synopsys site as well. Could anyone give me some advices? Many thanks in advance. W3Y
you can download tcl manual from the internet, or you can download a software named activetcl from "www.activestate.com" and install it, you will get a detailed tcl help document. Or I can send a tcl document which is written by synopsys to you if you privide your email address. Added (...)
I have install syn2005 in RedHat AS 4.0. when I start DC use this command dc_shell. It gives me the following message, and begain for waiting, I don't now why. synopsys tcl Syntax Checker -Version 1.0 Loading snps_tcl.pcx... Loading syn.pcx... scanning:stdin Anyone know why? Does the new DC (...)
Hi, If you have synopsys solvenet account, you can download tcl training manual from EST. Best Reagrds, chyau
In primepower(synopsys), where do we write the script? is it in VIM? if it is in vim..then how does it accept the syntax of tcl....?
for verification perl is most used n tcl is used in almost all tools of synopsys n soc encounter !! tcl is tool command language perl practical extraction and reporting language perl has strong text processing utility for automation of verification process like generation of stimulus (...)
Hi I am now learning synopsys DC... I need to know DC-tcl command If u know anybody plz send it her or thro my mail energeticdin(at)yahoo.co.in Dinesh Don't you have the synopsys DC documentation ?
Hi everybody, I use BuildGates to synthesize, I run script and the tools run into the bottom windows but I want to write it to a file to read. Ex in synopsys DC u can use: source ./scr/constraints.tcl > ./report/rpt.txt but in Cadence I can't do that. Pls help me. Thanks.
You should use Design Compiler (DC) of synopsys. Write a script and use tcl-mode of DC.
They are included in your synopsys distribution and it is called dc-transcript There is also a dc-to-Xg called db2xg
if you are defining link library then use remove_lib else unset link_library. Give synopsys_dc.setup as diff name i.e. synopsys.tcl and then source it.
List is a tcl standard data structure. You can use standard tcl command such as lindex, lappend, ...on it. Collection is synopsys's proprietary data structure behaves like pointer in C/C++. ----------------------------------------------------------------------------------------------- (...)
tcl script is what you used to run your tool, DC for example. SDC is "synopsys Design Constraint" file, this is the constraints that applied to your design. SDC typically used by timing driven place & route tool.
The following is copied from synopsys.com question is : 1)This program only find cells that connect to inout pins directly ,Is it enough and correct just only set_false_path with these cells. 2)From SOLD,just only four path exist ,input to output,input to FF/D,FF/clk to output and FF/CLK to FF/D. the path set by the following (...)
Hi I got a problem when leaning the tcl for synopsys tools.Why the follow command line is wrong. foreach my_port [filter \ { set_drive -rise 0.1 $my_port \ set_dirve -fall 0.1 $my_port \ } Thanks
in design analyzer, the original gui u can only use the synopsys script format of scr. whereas in design vision, it is cater for tcl script.


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