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106 Threads found on edaboard.com: Synthesis Encounter
Hi friends, I am using encounter 13.26 . After synthesis, I import the netlist/lef/lib/io/etc to encounter. But in the floorplan view, I can not see any module. Since I am trying to use Top-bottom hierarchical flow, and there are several modules in the design. I want to make one of them as a partition. The question is how can I view (...)
Hi, As the title of this topic indicates, I want to synthesise and P&R a design without buffers in order to observe the behaviour of long interconnects to the delay. Therefore, I want to know if there is any way to disable buffer insertion to my design, both at the stage of synthesis (Design Compiler - Synopsys) and the stage of place and route
Hi all, I am working on a DFT . its an academic project where iam using cadence tools - genus synthesis solution (formerly RTL compiler) for DFT and encounter test(ET) for ATPG. now the question is, after performing DFT synthesis, i was supposed to write ET scripts which were used by ET for generating testpatterns with the command : (...)
We really feel sorry for you, but what else can we do! Hi, When i am doing clock tree synthesis then encounter is automatically terminated. By showing this error. **ERROR: (ENCCK-1044): Due to earlier errors, failed to generate consistent RouteType FE_CTS_DEFAULT. Your post
Hi While doing HFNS i got the high fanout nets using the dbGet command. but when i give buffertree synthesis command it says, two nets have no driver so It shows an error message and it aborts the buffer tree synthesis operation. The net it is telling "no driver" is actually a pin of macro. Do i need to give any special command?
Hello, I'm designing a simple circuit using Multi Supply Voltage. I'm using synopsys Dc Compiler for synthesys, therefore I must use UPF. For the physical implementation I will use Cadence encounter which doesn't support UPF, but requires a CPF. Since my design is simple (I have only one power mode) the translation from UPF to CPF is sim
In choosing between design compiler and encounter RTL what are the points / features i should consider? In terms I want to know what points i should check while choosing synthesis tool for asic design? You could do an evaluation of each on your design, comparing QoR (timing, area, power). Cost will no doubt be im
Hi I want to know best synthesis tool for asic design. From web i have listed some like 1. Design Compiler by Synopsys 2. encounter RTL Compiler by Cadence Design Systems 3. HDL Designer by Mentor Graphics 4. TalusDesign by Magma Design Automation I know it might be difficult to say best because it might depends on what to implemen
Dear All, I have a .v file and i have done scan synthesis using RTL Compiler. Now how to approach for doing ATPG using the encounter TEST(ET)? Do I need to export the scan.def file to ET for doing atpg/ fault analysis? I don't know the exact command to do this export thing. Kindly Help ASAP.
Hi, I am new to APR so please excuse me if my questions seem lame. Should the netlist output from synthesis have VDD/VSS ? Also, Do I have to add Power rings in encounter to be able to place std cells ? As I do place but nothing appears in the layout . Thanks
The post synthesis netlist should ideally not give you any problems. Can you check whether the clocks and resets are correct?
STA can be run on 2 occasions : pre-layout & post-layout. Pre-layout STA requires the post synthesis netlist & constraints. Post-layout requires the P&R netlist, the constraints & the SPEF file generated from a tool like STAR RC. If you have a "gate level netlist form synthesis", then you must be doing pre-layout STA. You don't need anything else
Hi, I am getting an error while doing clock tree synthesis in encounter 10.1. It showing that **ERROR: (ENCCK-158): Cannot find output terms for clock clk_in/ANAIO. Here pad inastant name is "clk_in" and pin name is "ANAIO". CLock tree specifile started like AutoCTSRootPin clk_in/ANAIO NoGating rising #(for auto CTS on a net) Bu
Hi, I am getting an error while doing clock tree synthesis in encounter 10.1. It showing that **ERROR: (ENCCK-158): Cannot find output terms for clock clk_in/ANAIO. Here pad inastant name is "clk_in" and pin name is "ANAIO". CLock tree specifile started like AutoCTSRootPin clock clk_in/ANAIO
In RTL, clock buffers and MUXes are used to create a delay chain/tapped delay line. These are preserved in synthesis and hence they appear in the netlist. If this netlist is used, during Clock Tree synthesis (CTS) stage, the tool (SoC encounter) hangs and does not move forward saying that the clocks are already built and cannot be removed. (...)
hi friends, I have started working on cadence soc encounter. when I am writing code on verilog , no errors will be found when I am doing my synthesis. But when Iam writing a code in VHDL, lot of errors are found when iam doing my RTL synthesis. Is it cadence soc encounter will only work for VERILOG, or VHDL or both. Ramya
synthesis is done using RTL compiler from cadence, Design Compiler (DC) from synopsys. Routing is done by PNR tools Cadence encounter uses Nanorouter for routing. ICC also have it own routing engine. There are very good documents related to ASIC design are available at below link.
when i am using dc_compiler for synthesis i have a problem in passing dc_compiler files (netlist ,sdf) to encounter as i have to modify my netlist and make pin assignment in in , my Question is their a solution for this problem , as in large chip with huge IO how i can make the
There are many aspects to cause the size different, both tools are running with different optimization method, this is normal to have size different but not more than 20% different btw both. I only can guess the constraints in both could be different, e.g in synthesis you have use WLM, (top, enclosure, segmented) but i synthesis the RC are calcul
I'm running a synthesis using RTL Compiler and I need a captbl file for physical synthesis for the interconnect RC extraction models. I can find .ict files but I don't have a .captbl file. How can I create one of these or which software do I use?
Hi all, 1) Could you please let me know how can I consider timing-related constraints on place and route. In DC when we are performing synthesis, we can put a kind of constraint on the maximum delay between inputs and ouputs (e.g. delay between in1 and out1 not exceed X ps). I am wondering if there is a similar method in encouter? 2) I for
Hi everybody, When I check the design in RTL compiler 10.1 after synthesis, I get the following summary for my design. I know that Assigns are not good and should be removed before importing design in SoC encounter and I know how to do it. But my question is about the Constant hierarchical Pin(s). I don't know what those mean and if they a
i believe what the tool here is doing is correct. Basically synthesis is not only supposed to map the RTL to technology gates but perform optimization as well. Further in your case say 2 back to back inverters would give the same logic as output which was at the input stage thus a buffer. The same is what 6 inverters i.e.3 pairs of inverters are le
How do we do Physical synthesis using Cadence RTL Compiler?:?: For once i tried it with Physical synthesis command reference, it successfully completed with necessary flow.:| But i have not given any floorplan file for it.:-x How do i write a floorplan file specific to Physical synthesis.:?: Is there any good PDF available to write a (...)
I imagine the synthesis too indicate which latch made the issue, after that you need to read the RTL code to know what king of latch could implement the code, asynchronous set/reset, and if this kind of cell exist inside your liberty file.
I have inserted integrated clock gate cells in my design in DC and during clock tree synthesis, encounter inserts the CLK buffers before the clock gate. This causes the buffer to run, when there is no clock required. ANyone know how to move the clock buffers after the clock gate cells, so that they switch only when the circuit needs clock and save
Dear darockdr, logic synthesis with Cadence tools is performed using encounter RTL Compiler. To perform synthesis you need to provide the tool with the following information: list of HDL files composing your design, top-level entity (while launching the synthesis script), absolute path to the technology library of interest (...)
hai friend you can refer this document , i hope this might help you when you synthesis your design you will get the total power required your total no of cells thank u
Dear all, I am running in a problem while performing Clock Tree synthesis using Cadence encounter. I am using NanGate opencell 45nm standard-cell libraries. While editing the clock specification file, I got the following error, preceded by a warning: **WARN: (ENCCK-994): Cell BUF_X1 has no timing arc. Check The timing libraries. **ERROR: (E
In encounter RTL Complier, is it possible to specify the tool to use UVT (Ultra-high Threshold Voltage) standard cell library for module A and RVT standard cell libray for all other modules? Currently, I am using optLeakagePower in postroute stage of Place&Route. However, it seems that a significant portion of cells in module A not being replac
For clock, just let the encounter do it using these commands: createClockTreeSpec -output clk.spec clockDesign -specFile clk.spec cksynthesis For reset if you want to buffer it, make a copy of the clock spec file and change the clock name to the reset name. Then use these commands: clockDesign -specFile rst.spec ckSynthe
Hai , I have clock transition violations after Clock tree synthesis is over.skew and insertion delay are under control. Is there any command in encounter or Ic compiler to clone a clock net to fix tran violation?
For digital ASIC: RTL, Gate-level simulation and functional verification - IES (Waveform viewer - simvision), formal verification - IEF Logic synthesis - RC Compiler Layout synthesis - SOC encounter For analog ASIC: Schematic + Layout : Virtuoso Simulation : MMSIM
No, It can't be used for placement and routing. Cadence encounter RTL Compiler with Physical is a synthesis tool. It does physical aware synthesis that delivers real physical interconnect timing in the logic synthesis environment. For doing physical aware synthesis it call Encou
Hi hbeck, I hope you also used optDesign command in encounter. You should also take care of SI effects. pads are like memories, you directly instantiate them inside the code, but you need to provide timing & physical view, like std cell to synthesis & PnR tools.
In the clock synthesis phase, SOC encounter complains like below: ** Pin mcu_otp/pwd0/clk_src_gate/U1/Y is a crossover pin between Clock OSCX_CLK and OSC_CLK --- Overlapped subtree rooted at mcu_otp/pwd0/clk_gen/clk_gate/U19/Y: Excluded Term top/clk_gen/clk_gate/U15/B1 is found in clock OSC_CLK but NOT in clock OSCX_CLK. ..... **ERRO
Has anyone synthesized a design using more complex cells such as T or JK flip-flops or binary adders? I am successfully characterizing a T flip-flop using encounter Library Characterizer. I want to use this flip-flop to synthesize a simple counter netlist but RTL Compiler is unable to verify the function of the cell, and cannot use it. I want to
Hi everyone. I have designed a small digital block with verilog. Then I did the synthesis with synopsis DC. After that I generated the layout in Cadence SoC encounter with the STD cell lib provided by the foundry. Next I export the encounter layout into a GDS file. I want to import my GDS into cadence virtuoso layout editor to check (...)
Hi everyone. I have designed a small digital block with verilog. Then I did the synthesis with synopsis DC. After that I generated the layout in Cadence SoC encounter with the STD cell lib provided by the foundry. Next I export the encounter layout into a GDS file. I want to import my GDS into cadence virtuoso layout editor to check (...)
Maybe this can help: "At this step a VHDL net-list is also generated. It is recommended at this stage to run only few tests with the post-synthesis net-list, merely to verify the synthesis process did not fail on basic issues. A more intensive test scheme should be run on gate-level with timing on a post-layout
You are doing preCTS analysis and Clock tree synthesis, rt?? Clock tree analysis the min/max path where you r seeing?? As far i know it reports in Clock report nd log also for each clock in your design. The min/max path for the CTS is the min/max path clock is reaching to register. ie the shortest and longest path of the clock . For building clock
Hi, I am using encounter RC compiler to synthesize my verilog/vhdl files into gate-level netlists, using a standard cell library. However, the logic synthesis process only creates a synthesized .v file (output file) Is it possible to generate a .vhd synthesized file using RTL compiler? Thanks, Sambhav
PnR tools such as encounter can also dump a wireload model file (Command wireload) based on routing stats. This should be iterated with synthesis tools to get better WLMs. Anyways the first wireload model evolve from previous designs.
Hi When synthesize clock tree in SOC encounter, one needs to specify the clock tree spec, like the one below: MaxDelay 10ns MinDelay 0ns MaxSkew 200ps SinkMaxTran 400ps BufMaxTran 400ps Question: what is the resonable number to specify for each of the field? Why people care about the MaxDelay and MinDela
Hi, I have a question,when I use Cadence SOC encounter to create Clock Tree Specification, why does it show me "wrong number of argument to create ClockTreeSpec? How do we decide,create and get the file of clock tree specification?Thank you!
I am new to encounter RTL Compiler and I have created a simple circuit in Verilog in order to gain more understanding of the environment. The circuit is a 2-bit down-counter and this is the code used: module down_counter(out, clk); output out; input clk; reg out; always @(posedge clk) begin out <= out - 1; end endmodule The m
i have donloaded a verilog code in xilinx 8.1 i have encounter a module used for instance RAM128X1S_1 and ROM 256X1 this module is never defined or its code is not written anywhere is program synthesis report says Set user-defined property "INIT = 00000000000000000000000000000000" for instance is this module is automatically defined in us
hi i'm in an asic project . we use tsmc 090 standard cells. we generated rams using artisan ! we use synopsys design compiler (synthesis) first encounter(layout) calibre(lvs , drc etc) to perform post layout simulation on modelsim , and verilog to spice netlist translation using calibre v2lvs , we enter the verilog file generated by the
I am attempting to design a clock tree for a design with clock gating. I am having trouble understanding the syntax for the ctcsh. My design gates a clocks for power and functionality. In each case, devices clocked by the gated clock are expected to be synchronous with devices clocked by the ungated clock. Should I time through the enable/c
Hi, I have a question,when I use Cadence SOC encounter to create Clock Tree Specification, why does it show "wrong number of argument to create ClockTreeSpec to me? How do we decide,create and get the file of clock tree specification? when I use Cadence SOC encounter to do the Physical Design,which websites have *.sdc , *.lib, *.tlf, *.v,*.