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13 Threads found on edaboard.com: Target Skew
You cannot... you can just estimate. Your target insertion delay should be such that your skew is not very high and for that you will have to do some dummy runs. However, thumb rule says skew should be as low as possible. So for a design with 20MHz (50ns clock period) 0.5ns skew means 1% which might be acceptable depending (...)
hi, How Clock skew and latency of a design will change with respect to target clock period i mean, if i decrease/increase target clock period, how the skew/latency changes, if changes how/why they change? is skew/latency are depend on target clock period?
No DC will not do this. This needs to be done by the user. He has to estimate the target skew or uncertainty and give this to the tool. Normally we go with 10-15 percent clock period as uncertainty. But this depends on the design also.
Hi, It depends on lot of things... - Fanout of your clock which you cannot control - The cells your are using to build the tree. Try using higher drive cells. - Max tran limit you have set. If it is very tight it will increase your levels. - skew target - Also check your clock grouping to make sure your are not balancing the clocks which need no
Can you elaborate more on how CTS screws up? The latency value specified is picked by CTS as the skew target.
The highest clock frequency of design is 2M. Does 2ns trsnsition target tough for CTS? This is my first time to do CTS.
I usually add a clock uncertainty margin to account for expected OCV at synthesis / pre-cts (on top of expecteted skew and jitter margins.) OCV increases with delay of the non-common clock path, so consider that and your ASIC vendor's suggestions for the target process when increasing the clock uncertainty for OCV for different clocks.
i will go with 0.5ns, As skew is matter only when am thinking if my design has just met target freq.
quality of CTS engine depends on how low skew & latency values it is providing while maintaining the level of clock tree structree and hw many buffers its inserting so generally it is followed to give a 0ps target for both in first iteration and from this iteration reports, set the target for both parameters for next iterations,, but for (...)
How do we arrive at slew , derate values .I mean based on what slew limit are derates values are decided ?R they depends on technology nodes ? When clock gating helps in minimizing temperature then y we not consider clockgating helpful in minimizing leakage ? What r the factors that affect jitter ? why slew target should be met ? W
For a foundry process, you will have been given the Spice model for the target (normal) process and models for Fast and slow nmos and pmos. You should run simulations for all variations e.g. nmos pmos N N F N N F S N N S F F F S S S etc, etc
If we meet setup and hold,but if we not meet skew as given target skew this any problem.
1. Questions regarding the Synopsys Setup file synthesis. Why link lib and target lib is required and order of search path . 2. clock constraints like uncertainty, clock jitter, skew and etc. 3. explain about timing path. 4. how to specify IO delays. 5. Max dealy significance. 6. Optimization techniques. Best of luck.. Regards,