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420 Threads found on Template
You can set all the defaults from pull-down "Options" -> "Design template" The title blocks are in \tools\capture\library\CAPSYM.OLB Open the library to see the "stock" title blocks. Use as-is or copy and modify your own
I want to scan finger library of R305 module.5 finger images are already enrolled in that module.I want to write code for scanning and displaying whether "found" or "not found" So,once i collect finger image,what operation i need to perform?,whether i need to make template/character file or need not make it?
Welcome Naveenkumar.G.K, Congratulations on compiling such a paper -- it's a bit of work, and you've obviously put alot of thought and effort into it. Actually, he didn't wrote the paper, he used it as design template. @Naveenkumar.G.K How did you simulated your antenna and what software are you using?
on the other hand, you can add your own parameter name and put "=YourOwn" in template file (schdot)
There are few or no ready-to-use C code examples on the Web about implementation of (secure) file transfer protocols with the ESP8266 (ftp, ssh, etc ...) working as client. Most of them cover the HTTP so that based on these source-codes as a template for your project, you would certainly send this via POST command, but on the file server-side you s
Here is a forum proposed to host technical discussions; I do not feel encouraged to help someone who can take a degree without even trying to start a single line of code. There are a lot of examples on Edaboard with which you could start as template. If you have some knowledge in programming you'll see that it is possible to do that.
The same diodes + voltage divider level shift circuit can be found in many controller ICs with internal error amplifier. May be they just copied a design template. I don't see the purpose of asking "what's the purpose of". Just take it as is. The specified characteristic is achieved with this circuit in place.
If you are doing negative numbers, why are you using unsigned type? Also, why are you using all asynchronous logic constructs? why no synchronous logic, or at least, why are you not using the template? your synchronous logic descriptions will not currently synthesise, as you are creating a latch, not a register, and you're going to create a logic l
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Hi, I am facing problem in finding the input impedance of a unit cell FSS in CST with FSS unit cell template. BY applying unit cell boundary conditions and floquet ports and then simulating with frequency domain solver, I get the S parameters but the input impedance is not calculated. BY simulating simultaneously with floquet ports and waveguide
Quartus synthesizes the miso output register code because it can be rewritten as regular synchronous register description according to the template. Just pull-out rising_edge(clk). There are however many latches generated and missing sensitivity list entries will probably cause simulation to synthesis mismatch. Don't know why the design is wr
Hello everyone, I am trying to simulate a unit cell by eigenmode solver in CST 2014. I use steps as: "Eigenmode solver -> Parameter Sweep -> Results template -> 2D, 3D Field results -> 3D eigenmode result". I obtained the plot of "frequency vs phase". My question is: How can i obtain the final dispersion diagram (frequency vs beta)
Use the conventional equation y=const* (x^2) and plot out the curves manually. Use different values for the const to get different shapes. Then make a template and use that ...
Use assignment editor rather than pin planner, or check the .qsf file to see if there is another variable handling these pins. You are perhaps using as template a design not 'empty', so something is likely already assigned to those pins as they said above.
You can do it with a 3rd party pre-processor that generates a new file from a template. At one point I had one that let me embed python code in a VHDL/Verilog file for the purpose of code generation. Yes, you can do that. But I presume the thread topic is learning valid VHDL syntax rather than using a non-portable method to
A better solution!? How about using the STANDARD template for a resetable FF. Maybe you should go find the Altera and Xilinx documents on writing synthesizable code. @lh- , Hear what they are telling you; the the right thing to do is to take advantage of templates provided by FPGA manufacturers, which have either th
You spent an excessive amount of lines of code just to initialize unused (at least not yet) resources of the core and their respective comments, whereas most elementary assignments are not present in your code, such as TRISB for example. You should consider using a simplest template to start a simple task as you want to do.
Hi all, I am new to ADS and looking to simulate a RF power detector with a Schottky diode. I have created the diode model (see attached below) with all parasitic elements, but am struggling to simulate the whole circuit. Which solver/template should I use to do so ? Ideally, I'd like to get a Vout vs. RFpower plot and the time response (Vout vs
As a concept, it is odd to intentionally create an async reset that is actually a sync reset. The Verilog always construct describes an asynchronous reset. You might say that it's odd in some way that an asynchronous input is described by a negedge event. The synthesis template for a edge triggered register with asynchronous
I'm not expert on FPGA fields, but every time I see someone requesting a peculiar control system that could be typically implemented on uCs ( I mean, no strict requirement to do it in hard logic ) I feel the lack of prior knowledge background on both subjects, or at least no previous effort to start from template/scratch. I would recommend you give
Yes it happens if you do not tell CST to keep record of the results. To do this use template based post processing and define there the results you want to record and then you will be able to see the results in tables of CST tree
Hi, I want to make a prototype of a human skin painting machine for painting small designs i.e, painting small patterns on the arm/ face for kids, with a few template designs to choose from. I have a know-how about some basic electronics/ micro-controllers and computer vision but I need to know what else should I study to help me make this des
Hi; I ask how can i use the template of 'load pull technique ' in ADS to display the PAE of my amplifier . In fact, i design an amplifier class AB and now i shoud enhance the efficiency so i should use the load pull technique in ADS . However, when i use the template(design guide-->load pull) after that i delete the existing transistor and it's
Hi; I ask how can i use the template of 'load pull technique ' in ADS to display the PAE of my amplifier . In fact, i design an amplifier class AB and now i shoud enhance the efficiency so i should use the load pull technique in ADS . However, when i use the template(design guide-->load pull) after that i delete the existing transistor and it's
Hi; I ask how can i use the template of 'load pull technique ' in ADS to display the PAE of my amplifier . In fact, i design an amplifier class AB and now i shoud enhance the efficiency so i should use the load pull technique in ADS . However, when i use the template(design guide-->load pull) after that i delete the existing transistor and it's
do you want to implement the error amplifier in software or in hardware.? If in software, then that is historically a hard job, unless arduino has some template software that you can shove values into. I send you example of voltage mode control, its not buck but you get to the point, its in ltspice. ltspice is free download. just change file
Hi all, I was wondering if anyone has any suggestions for how to best perform cost trade-off calculations and analysis for different electronic circuits. More specifically, I am wondering if anyone uses a specific template every time that you or your company decide to analyze the cost trade-off between electronic circuits. For example, I had
I must implement in vhdl a neural network capable of recognizing these characters: left arrow, right arrow, up arrow and down arrow. I need to use as a template matrix 7 * 5. I also to be and code in Matlab for it.
Epitaxy is meant to add to a crystalline structure and keep the lattice form. CVD only needs to deposit the material and is not expected to grow continuously from an underlayer "template". Same for PVD, sputtering, etc.
Your controller schematic isn't but a general template, you need to put in specific component combinations for Z1 and Z2 to make it an actual controller, e.g. a PI. You also need to correct the driver polarity to inverting for the present switcher topology. There should be a specification of intended control behavior, particularly bandwidth of t
Here is my RTOS test code, i want to run two threads to blink two different LEDs at different rates. I am using Keil RTX, I feel its better in use than freeRTOS. /*---------------------------------------------------------------------------- * CMSIS-RTOS 'main' function template *-------------------------------------------------------------
Hi everyone, Please, can you help me how numeric division between two 1D results in CST MICROWAVE STUODIO could be done? I cant find such option in postprocessing template. Thank you for any advice.
// My systemC using template class code is below. When I do C-synthesis on vivado, I get the Error Please anyone help sooner where the problem resides. #include "systemc.h" template SC_MODULE(DF_ADDER) { sc_fifo_in input1; sc_fifo_in input2; sc_fifo_out output; void process() { //while(1) out
Hi, According to Dogan Ibrahim book (Advanced PIC projects),i'm tryning to experiment the USB HID project. I used easypic7 to interface PIC18F4550 TO PC using USB. The project run's ok in similation by using a GUI interface template EasyHid in VB6 and in VBexpress 2010, but in real hardware nothing changes in PORTB. NB: the jumper J12 in right p
In such cases, a good practice is to subdivide the whole design into different layers at the programing level and split the hardware logic into functional modules as much as possible, so that a migration to another vendor platform could be easiest accomplished from scratch through the template of some wizard tool at the IDE.
I am implementing address translation for old nibble-mode DRAM input signals. This DRAM receives address in two halves, MSB half on falling edge of /RAS and then the LSB half on /CAS falling edge. After /CAS going down the first time DRAM outputs data. /CAS will go down three more times (for a total of four times) to get consecutive data out, bu
you have *.max file( layout plus file) or *.brd file ( allegro PCB editor file)? for *.max you can save it as a template file and load the new netlist in to this template
Hi all, i have started writing skill for CDF parameters for the first time.I am having a template seeing that i am writing the questions are as below. 1)How to add the button.For cyclic we can added choices.But where as for the Button it is not taking the choices.Please write a small program if u know it. 2)I am creating or ad
As far as I can understand that the hardware required to implement the code below is not supported in Xilinx ISE Web Pack. I'm trying to implement only the functionality of the 8-bit adder using an always block. Here's the code: module Addr_8bit(Clk, Rst, En, LEDOut ); input Clk; input Rst; input
Your question needs clarification, please. Do you refer to: (a) threads which appear in pcb design schematics, templates, etc., or (b) discussions about cmos design at this forum which you are asking how to delete? If 'a' then please specify the design environment, template, etc. (Include a picture if possible.) If 'b' then the usual answer is t
It can be achieved by choosing the Thermal------Thermal Loss Calcuation in the template based post processing. Hope this could help you.
Hi, I am new to Modelsim. I find there is a test bench template, but I don't find how to create it. Please see the picture. No matter what I add to the 'Design Unit Name', the 'Next' tab never turns to black. The small Verilog module has compiled successfully. Could you tell me how to create a test bench using the wizard for Verilog code
Hi, I am working on this also and have some difficulty in getting accurate results. However i hope i can be of some help. From Eigenmode solver -> Parameter Sweep -> Results template -> 2D, 3D Field results -> 3D eigenmode result -> choose modes you want. The results should be at the 'tables' section.
Please don't use upper case letters, it is considered 'shouting'. What doesn't work properly? Please tell us the symptoms. Start by copying the template provided by Microchip and add your code to it. Also add comments so we can see what your lines of code are supposed to do. From what I can see, this has nothing to do with an LCD, did you mean LED
Hi, I am trying to run a simple hello world application by using New Nios II Application and BSP from template option in NiosII EDS. After selecting my sopcinfo file, choosing my sample project (hello world) when I click on build project to generate my elf file, I get the following error : alt_sys_init.c:(.text+0xb8): undefined reference to `
Hi, I search iet microwaves antennas propagation template but I can't find it, can anyone help me about that? I really need for this template.
Sir, what should i do then ? Thank you your help. Typical s-parameters simulation setup. ( You can also use template of ADS ) 117973117974
I have made a design using the Nios II core in qsys. After compiling successfully, I proceed to Nios2EDS to create a new Nios II application and BSP from template. After selecting my .spocinfo file and clicking on finish, I get the following error : Failed to execute: ./create-this-bsp --cpu-name cpu --no-make Does this mean my h
There is an option to do that, but not so much elegant. You can use 2 uC´s at each side, one sending end other receiving. The low cost familly CY8C24 allow synthesize a limited number of analog and digital systems inside, and contais a lot of template modules such as A/D, D/A, UART, SPI, etc... It is important to know how much speed is required
Dear Members, I am desiging a simple rectangular substrate filled waveguide in CST MWS using Si Wafer. The dimensions of the wafer are in um and the center frequency is 10 THz. I have selected the optical template in CST. I am getting following error when assigning the relevant thickness of wafer materials i.e. SiO2 (1.5 um)+Si(380 um)+SiO2(1.5