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42 Threads found on edaboard.com: Test Plan
Has anyone ever tried this schematic done by Swagatam I like his circuits I have some of the parts of the circuit I plan to build the high frequency section of it I think the only thing I wouldnt have is the 20uf caps at the input I plan to just use 24v to test it, Can I use 2 10 uf 400v caps at the input thats all I have now after a while I (...)
Hi, I want to test an LNA IC. I want to use supply of 0.7V and make it as low noise as possible. I plan to use a 6V lead acid battery and then use a voltage regulator as follows Can anybody suggest better ways? The lab power supplies that I have make the noise figure 1dB worse.
Dear Board i ve Canalyzer with me and i know basic CAPL scripting. with CAPL i can do some test cases successfully for easy working. But i need to implement image processing but i dont know how to do it with CAPL. so, i plan to take canalyzer COM server to VB6.0 and send some message from there to vector canalyzer (in physical vehicle network)
Hi, I already design a LNA schematic and layout, so far so good. Now, I plan to make it as a differential pair LNA... I had some idea about the schematic and test bench, but it does not work very good specially when it comes to layout. Can anybody introduce me the references I can use for finding the structure os schematic and also the (...)
I have taped out a chip for low power ECG acquisition. I have to plan to test the chip when it comes back. Regarding the same, I would like to have some information about the test set-up used for the testing if the chip. What are the instruments used for the testing -company and instrument number, (...)
I've not used Altera SERDES, but designed many SERDES in the 70's (DS1 BER test sets etc) 1) Normally bit clock VCO runs at 2f with quadrature 1f outputs, quadrature (90deg) 1clocks should be available. Pre-Comp, may help improve SNR or jitter reduction, but watch out for ISI and group delay distortion. plan on doing BER margin
You need to design a testbench that covers as many cases as possible. They are still referred to as testbenches, even when using UVM. UVM is just a system verilog library of common module behaviour and checkers. So its not a method in itself - a poor testbench using UVM is still a port testbench. You need to think about your (...)
Hello, I would like to plan a test PCB with multiple components that will interface to automatic tester with PCI edge connector. Since I would like to conduct test of up to 300VDC, I want to know what is the maximum voltage allowed between 2 adjacent PCI edge connector on PCB? How is it dependent on temperature? (...)
hi guys i wrote a big program for an electronic system based on pic microcontroller after testing i didnt find any problem but im going to design a test plan to will sure system hasnt problem how must be design an embedded software test plan. please help:roll::roll: Hi, I have some experience of this. (...)
Hi All, I need some advice if possible on how to make the first investigations on a system for noise cancellation/ noise removal. My plan is to place a speaker and a microphone (standard speaker/mike, low cost, non callibrated type) in a room, connect it to a PC audiocard and test if it can attenuate the sound level in the room, being speach
What battery/battery bank capacity you plan to use with this 600W or 1000W inverter ? What working time and battery/battery bank life you expect ? In bottom right corner of circuit diagram, you have author email address. Its best to hear him, because he try and test device. Best regards, Peter
My input signal is a multi-channel/carrier OFDM. Each channel have 5MHz bandwitdh. Now, I would like to simulate a 2-tone test for its IMD. I plan to measure the 3rd order at say +/-0.2 MHz offsets from the edge (4.8MHz and 5.2MHz). My computation is a spacing of Fcarrier +/-1.8GHz, in order to create the 3rd order tones. Is this correct?
Hi i have one interview question.....? how you verify your mod10counter.....? how u write test cases and verification plan for u r mod10 counter.....? i need exact answer for this.......?
There are EMC standards for ingress that a designer needs to be aware of for interference. THese exist in Europe (CE) USA (FCC) and Japan as well as other nations. We used to test for ingress with AC lines and brush type electric motors with data cables next to it for measuring coupling. So I would plan on designing a shield from ingress. THis can
how to make test plan for asynchronous fifo which have write clock =250 Mhz and read =125Mhz specification: wr , wr_clk, rd, rd_signal, data bit 8bits, deapth of FIFO 16 bit
oh, that some basic stuff: 1- write spec/verification plan 2- write RTL & TB 3- write tests (simulation) 4- this code could test ON FPGA or CPLD (two differents technologies, depend of your goal) 5- synthesis/DFT to your technology target 6- place/CTS/hold/Route 7- STA 8- along 5-6-7, LEC & ATPG 1 to 3 is mainly the frontend 5 to (...)
test plan : It is your plan to test the DUT(Design Under test). That is, all the necessary tests to be done on the DUT to check all the features. test Bench : It is module to give the stimulus (input) to the DUT. In this you will drive the values as per your requirement. (...)
I was asked "How to verify a 16 bit adder and a 256 bit counter." I was asked how I will develop a test plan to effectively test the above circuits. They dont want the exhaustive testing of the circuit. Please share your answers. Many Thanks!
Could anyone suggest proper arrangement for construction of barrier arm Any mechanical dimension construction we need We have made test setup Before without attachment of the arm we are found out that gear box and arm attachment rod is well working according to plan. But when we attach the arm then the rod attachment with arm is not stable as
Hi..I'm working on an individual project..I dont have acess to a VNA or spectrum there anyway I can test an antenna??? Moreover, for a source I plan to use acommerically available 2.4 GHz device, like a WiFi device or it possible to do it?? If any of the experienced members can throw some light, it'll be really helpful.
Hi, I am planning to start a project called "Green power from paddling". The plan is to install a dynamo in a bicycle with a rechargeable battery to store the electricity generated by paddling. I want to test if a person drives a bicycle for 1hr, how much electricity he can produce and finally store in the battery. So I have got (...)
Does anyone have got experience with BOR reset on PIC microcontroller? How can I test at program level that a BOR reset occured? I plan to use that for end of battery life. Thanks for your input.
But I think Verification plan is for whole system verification and test plan is for specific tests just like FIFO , Registers , Path and all.we can say that testplans are subset of Verification plan
Look here:
Have another evaluation board, which is a "THRU" structure. This evaluation board should have the same PCB traces as your eval board minus the DUT (device under test). Hook this board up to your scope with the same cables, etc. you plan to evaluate your actual product. If your set up is good, you should just see the jitter from the scope or your
Hi All, I need to plan a collection and startegy to test a WIMAX Network with End to End testing. This means that all the components of the Network such as AAA, DHCP etc are attached and i have to check End to End functionality of the system also in extreme conditions, in various configurations. I have to check it only from the (...)
to have to a better estimation of the verification quality, you may need add assertions for the functional features, also you need ask help for some advanced guys to review your test plan. The tool is not a big deal, but the way how to use them is.
use matlab software to test.
You sure the device failed? For instance: if you try to test the Vgs before Vds with the Cgs input you closed the channel of the device and so you could measure a short circuit at the drain side. That doesnt mean the LDMOS failed of course
Dear All I want to develop a drive test tool in very basic form. That is I want to get network parameters like RSSI and few others and plot them real time or else. Sugest me which handset should I used and what should be development plan. Regards Junaid
Hi, aditya_vij Why do you plan to test stuck-at fault in RTL phase? After synthesis and P&R, the wire name and the latch name will change. You can't ensure the fault coverage in RTL phase is equal in the Netlist phase.
Actually I plan to test the 2 digits BCD counter display on 7 seg. (in circuit I used two 7493s). I want to use (your) counter as a module and other module will call this module to run 2 digits BCD counter display on 7 seg. How to do. Pls..
I have to work on a realtime system and plan to build a miniature helicopter.Actually i have to test a MIMO Control System and for that purpose i have chosen to design a miniature helicopter model.I want to simulate the design equations in Simulink and to apply it practically on the helicopter.I have seen three four websites but all of them are sel
Hi All, I designed a linear PA for my school project. However I am experiencing problems with the test board layout using Autocad. I am trying to use FR4 substrate, but I don?t know the thickness of each layer, the size of via and component dimensions (cap, inductor..)?Can someone please give me some advise, or if someone can share some project
can anyone tell me good website which provide me sample netlist to asic design flow, so that i can do only P & R, is there any sample verification modules , which talks abt verification plan , test plan , test cases waiting for good reply
Ka-band freq 20-30 Ghz, Need to know how to setup the RF test equipment to do spot beam and gateway testing? Any suggestion...Thanks.
On an embedded test-platform we have to configure a remote @ltera Cyclone device via its JTAG chain. Our test-platform also has an @ltera Cyclone fpga with a NIOS I SOC. We like to program the remote Cyclone via its JTAG. Right now we think the best method is to port the @ltera Jrunner software to the NIOS I. Questions: 1- has anybo
Has anyone actually prepared a test plan for CE compliance for medical equipment, specifically with regards to RF immunity? I have not had to do this before for this type of equipment Specific standards, limits and clauses etc. Any help would be good :R
I have three rfPIC12F675F and the corresponding receivers. I plan to test them but I haven't bought the components yet. Keep in touch
have anybody been involved in designing a PRBS generator above 500 Mbps for test and measurement equipment for optical communications? i want to design a 2.5 Gbps PRBS (2^7-1), but none experience in this field yet... any schematics, links or tips about this welcome! regards, rfmw
I plan test stacks from Rabbit and Atmel