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142 Threads found on edaboard.com: The Designers Guide
Hi, I am a beginner to RF design, but I want to know where to start when designing a broadband impedance matching network. I want to make 1W FM amplifier 88-108MHz using RD01MUS1 mosfet. I have the s-parameters, so what are the calculations I need to make a matching network. What type of matching network can be best used in this situation? (
Is there any way to simulate the hybrid parameters of the HBT transistor in ADS ? or is there any function in ADS that can convert the s-parameters to h-parameters ? My second question is about cut-off frequency. In the common emitter configuration, how can we obtain ft vs Ic in ADS ? (...)
I have a question relating to how an eye diagram is built step by step. I read documents about eye diagram. 1. For ISI, the eye is formed by: superimposing successive waveforms to form a composite image But, i don't know based on what criteria they cut a certain waveform of falling an
Hi All, the Nyquist criteria which is described in various undergraduate textbooks is for single input and single output. there exists a similar Nyquist criteria for MIMO systems. Atleast a google search presents a lot of results. But I have difficulty in its application. there are opamp based circuits which have MIMO loops. Example: (...)
Hi guys, In the documentation that I have in my possession there is no information about the ft of the transistors. Is there any way to estimate the ft of each transistors in my process? Through simulation for example. Regards.
Regarding the gm/Id paper by Tiwari page 21, the needed gm was calculated to be 12.6mA/V then on page 22 the gm/Id is calculated to be 6.3 V^-1 when the max drain current available i
Hi, I am trying to do something new to an existing VCO architecture and I found an improvement in the phase noise. Though I am not able to mathematically (I am able it only intuitively) explain the improvement at this point in time, I would like to know if PSS results are accurate enough. the question might sound vague, (...)
Hi, all of the model parameters for any transistors are simulated and stored. there is a method for extracting the parameters in virtuoso w/ spectre. Maybe check this link: I remember doing this with a dc sweep simulation and then going to Results Browser and reviewing
Simply drive DUT by Iin or Iin_plus and Iin_minus. then measure Iout+j*Qout or (Iout_plus-Iout_minus)+j*(Qout_plus-Qout_minus). Here you should use PSS/PAC
Hey guys, I was wondering where a design variable "frequency" gets generated in transient analysis in Cadence ADE (spectre) when I do a transient simulation of a set of devices using only behavioral VerilogA models and a Ipulse/current pulse. All the items in the simulation are behavioral models, and there is no "frequency" (...)
See the followings.
A ring oscillator with an odd count of inverters will always oscillate, because of the 180° phase shift. If you want to add phase shift to your Verilog-A inverters, perhaps this example could help, s. pp. 199 ff.
I want to derive third order input intercept point (IIP3) for my designed low noise amplifier (LNA). What I observed in the many IEEE transaction LNA paper, they used Volterra Series Analysis for deriving the IIP3 equation for their LNA. Which is the best text book for deriving IIP3 for our LNA and where (...)
Hi, In Phillips' paper: am quite baffled by his comment "impulse response of the phase deviation phi(t) can be approximated with a unit step s(t)". Why and how to explain that? Further, how to derive equation (6) from
Hmm - the way you talk it sounds like you expect all these processes to act sequentially, like a C program. It wont. Have you got a sketch of circuit from before you write any code?
Does anybody download "Modeling Jitter in PLL-based Frequency Synthesizers" from and test it in cadence? How to simulate it? can you send me the project in cadence? thanks!
linting checks just guide to have cleaner RTL code, before to read them by synthesis tool. the synthesis tool will also indicate some warning and also errors about the RTL code. But some designers work only as frontend design and some ones as backend design (...)
Like if I'm doing a transient sim and my freq variable is "Freq" I'd just refer to the freq as VAR("Freq").Use xval() function. See the followings.
You are asking about other forums while already in a forum... Forum-ception!! Try this : the Designer's guide Community Forum
ic6 doesn't start I have installed cadence ic6 suse 11.2 when I type icfb& or virtuoso , cadence doesn't start and gives the following error Qt Warning: X Error: BadMatch (invalid parameter attributes) 8 Extension: 150 (RENDER) Minor opcode: 4 (RenderCreatePicture)
Could you please suggest me if you aware of freely available verilogAMS simulators in online? Don't know, sorry. Perhaps ask in the a.m. community!
but i have plot Z11 Vs frequency not S11. i guess Z11 will give me the input impedance not the S11, if i am wrong than please guide me. the large/small value difficulty in reading your plots shows why antenna designers do NOT use these Z parameters. It will be much easier when you start (...)
pulldown primitive gave me some issues during synthesis long back. According to some resources, pulldown is supported in Verilog AMS, but not in Verilog-A. Please checkout this link : the Designer's guide Community Forum - Req example of pulldown command in VerilogA A solution i
check these discussions the Designer's guide Community Forum - what wrong with the CadenceIC? *Error* Unable to establish connection with WaveScan - Cadence Community
ADS can calculate group delay as far as I know. the rest you should be able to implement into an equation and plot.
Consider eigen mode of 1/(1-jw), that is, Inverse Fourier Transformation. It is "exp(t)". the Designer's guide Community Forum - Bode Diagram of Conditionally Stable System
Cadence doesn't like floating nodes... That's why connect a 1GOhm to each node and try to set the initial node voltages as 0 or 1 V etc..
What is the difference between phase noise in rad and dBc/Hz. I would like to know how to convert radians into dBc/Hz. thanks in advance :)
there is an article on the website the Designer's guide Community - A Resource for Analog, RF, and Mixed-Signal Circuit designers by Ken Kundert entitled 'Modeling dielectric absorption in capacitors' that may be of use. It includes a number of references. Guessing from the nature of your (...)
See the Designer's guide Community Forum - how to estimate the PSD of a complex signal in MATLAB
Sampled Mode exists in PAC and PXF of Cadence Spectre. This mode is similar to "timedomain" mode in Pnoise Analysis of Cadence Spectre. the Designer's guide Community Forum - switched capacitor integrator noise simulation results However I can't get reasonable results for
You had better post your question in the following since your question is regarding Cadence's tool. the Designer's guide Community Forum - Index RF Design - Cadence Community
I don't know spectrum() function in DFII 5.1.41. But it seems that there is no difference between spectrum() function and dft() function. By the way, new waveform viewer, ViVA provide function sets for evaluation of ADC. the Designer's guide Community Forum - snr of adc calcu
Use @timer(). @(timer(period/2+phase, period/2)) state= !state; V(vout) <+ V(vdd,vss) * transition(state, 0.0, tr, tf); end Also see the Designer's guide Community Forum - verilog A code for 16:1 mux My cadence
Use S-parameter of Touchstone format. the Designer's guide Community Forum - conversion of .s8p into SpectreRF netlist
See the followings. the Designer's guide Community Forum - Simulation Setup for Varactor C-V and Q-freq curve the Designer's guide Community Forum - Inductance extraction: L reduce with frequency?
See the Designer's guide Community Forum - Interpretation of Minimal value in LSB-Noise of Crystal Oscillator
check these links
See the Designer's guide Community Forum - Two tone test for transmitter / PA
See my appends in the Designer's guide Community Forum - RF circuit Dc bias question
See the followings. the Designer's guide Community Forum - Mismatch Parameters don't change in MonteCarlo of Cadence Spectre the Designer's guide Community Forum - Size Dependent Mismatch Variation's Description don't
Use "case ~ endcase" statement in Verilog-A code. See the followings. the Designer's guide Community Forum - verilog A code for 16:1 mux
I am frankly waiting for your help~~~Do you think there is anyone who can answer with your poor descriptions. This is also very true for the Designer's guide Community Forum - needs your comment: how to take power supply noise into account for PLL d
the Designer's guide Community Forum - Spectre search option
See the followings. the Designer's guide Community Forum - PRBS pattern for eye diagram USB FS driver... the Designer's guide Community Forum - Automation of Eye Aperture Ratio Measurement [url=www.desi
Yes Novice, the CAD tools can take care of the algorithms and stuff like that. But each command for a tool will have several options...these options will make a difference how the tool perceives a task. At the end of the day a tool needs to be told what it must do...thats where we (...)
See the followings.
hi I find a statement in Verilog-A VCO, just as: phase_nonlin = `M_TWO_PI * vco_gain * idtmod ( V(vin), 0, 1000.0, 0.0); I don't know why use the function idtmod(), and I cannot understand the meanings about this function in verilogA mannual. who can help me?
See the followings. the Designer's guide Community Forum - phase noise of ring oscillator using spectre the Designer's guide Community Forum - phase noise of ring oscillator using spectre [url=www
tran.tran.trn "For Spectre writing PSF data: setenv PSF_WRITE_CHUNK_MODE_ON true" You are using SST2 output format. the environment variable only works for PSF output format. See


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