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# The Designers Guide

142 Threads found on edaboard.com: The Designers Guide

## Design broadband matching network for amp - beginner

See the followings.

## [Moved]: Simulation of H-paramters and cut off frequency of HBT transister in ADS

Is there any way to simulate the hybrid parameters of the HBT transistor in ADS ? or is there any function in ADS that can convert the s-parameters to h-parameters ? My second question is about cut-off frequency. In the common emitter configuration, how can we obtain ft vs Ic in ADS ? (...)

## Eye diagram formation

I have a question relating to how an eye diagram is built step by step. I read documents about eye diagram. 1. For ISI, the eye is formed by: superimposing successive waveforms to form a composite image But, i don't know based on what criteria they cut a certain waveform of falling an

## Nyquist stability criteria for MIMO systems

Is the above rule a sufficient condition for MIMO feedback stability?You can not understand contents I posted at all. Modern control theory is surely useful for judging stability of MIMO System. Your complex filter is formulated by using state space variable equations. So modern control theory is straight for

## ft of a transistor - non existent in the documentation.

HI pancho, thanks for the links but let me ask you if you're posting those links randomly?What do you want to know ? Can you tell me where is those links are some useful information about how to get the fmax of a MOSFET?What do you want to know ? Evaluation of fmax is very easy. Sim

Regarding the gm/Id paper by Tiwari page 21, the needed gm was calculated to be 12.6mA/V then on page 22 the gm/Id is calculated to be 6.3 V^-1 when the max drain current available i

## Is it possible to judge the improvement in the phase noise based on the pss sim?

Hi, I am trying to do something new to an existing VCO architecture and I found an improvement in the phase noise. Though I am not able to mathematically (I am able it only intuitively) explain the improvement at this point in time, I would like to know if PSS results are accurate enough. the question might sound vague, (...)

## How to plot transit frequency in virtuoso

Hi, all of the model parameters for any transistors are simulated and stored. there is a method for extracting the parameters in virtuoso w/ spectre. Maybe check this link: I remember doing this with a dc sweep simulation and then going to Results Browser and reviewing

## How to measure IIP3 and SFDR of a complex filter in spectre?

Simply drive DUT by Iin or Iin_plus and Iin_minus. then measure Iout+j*Qout or (Iout_plus-Iout_minus)+j*(Qout_plus-Qout_minus). Here you should use PSS/PAC

Hey guys, I was wondering where a design variable "frequency" gets generated in transient analysis in Cadence ADE (spectre) when I do a transient simulation of a set of devices using only behavioral VerilogA models and a Ipulse/current pulse. All the items in the simulation are behavioral models, and there is no "frequency" (...)

## [Moved]: S parameters and adaption and stabilité ?

See the followings.

## Ring-oscillator Verilog A

A ring oscillator with an odd count of inverters will always oscillate, because of the 180° phase shift. If you want to add phase shift to your Verilog-A inverters, perhaps this example could help, s. pp. 199 ff.

## Queries on deriving the equation of IIP3

I want to derive third order input intercept point (IIP3) for my designed low noise amplifier (LNA). What I observed in the many IEEE transaction LNA paper, they used Volterra Series Analysis for deriving the IIP3 equation for their LNA. Which is the best text book for deriving IIP3 for our LNA and where (...)

## PSD of The Phase of the Oscillator

Hi, In Phillips' paper: am quite baffled by his comment "impulse response of the phase deviation phi(t) can be approximated with a unit step s(t)". Why and how to explain that? Further, how to derive equation (6) from

## VHDL: operations on bit vectors

Hmm - the way you talk it sounds like you expect all these processes to act sequentially, like a C program. It wont. Have you got a sketch of circuit from before you write any code?

## Modeling Jitter in PLL-based Frequency Synthesizers

Does anybody download "Modeling Jitter in PLL-based Frequency Synthesizers" from and test it in cadence? How to simulate it? can you send me the project in cadence? thanks!

linting checks just guide to have cleaner RTL code, before to read them by synthesis tool. the synthesis tool will also indicate some warning and also errors about the RTL code. But some designers work only as frontend design and some ones as backend design (...)

## Cadence Virtuoso AC Sweep: How to use frequency in calculator

Like if I'm doing a transient sim and my freq variable is "Freq" I'd just refer to the freq as VAR("Freq").Use xval() function. See the followings.

## famous Electronic Enginering community or forum

You are asking about other forums while already in a forum... Forum-ception!! Try this : the Designer's guide Community Forum

## Problem with starting Cadence IC6 SuSe 11.2

ic6 doesn't start I have installed cadence ic6 suse 11.2 when I type icfb& or virtuoso , cadence doesn't start and gives the following error Qt Warning: X Error: BadMatch (invalid parameter attributes) 8 Extension: 150 (RENDER) Minor opcode: 4 (RenderCreatePicture)

## getting started with verilog AMS.

Could you please suggest me if you aware of freely available verilogAMS simulators in online? Don't know, sorry. Perhaps ask in the a.m. community!

## Input impedance vs frequency

but i have plot Z11 Vs frequency not S11. i guess Z11 will give me the input impedance not the S11, if i am wrong than please guide me. the large/small value difficulty in reading your plots shows why antenna designers do NOT use these Z parameters. It will be much easier when you start (...)

## pulldown function in VerilogA

pulldown primitive gave me some issues during synthesis long back. According to some resources, pulldown is supported in Verilog AMS, but not in Verilog-A. Please checkout this link : the Designer's guide Community Forum - Req example of pulldown command in VerilogA A solution i

check these discussions the Designer's guide Community Forum - what wrong with the CadenceIC? *Error* Unable to establish connection with WaveScan - Cadence Community

## how simulate Q factor in ADS simulator?

ADS can calculate group delay as far as I know. the rest you should be able to implement into an equation and plot.

## Laplace transform and fourier transform

Consider eigen mode of 1/(1-jw), that is, Inverse Fourier Transformation. It is "exp(t)". the Designer's guide Community Forum - Bode Diagram of Conditionally Stable System

## why do 3 winding mutual inductors get unstable

Hello, My simulation schematic is a voltage source stimulating an inductor L0, coupled to another 2 inductors (L1 and L2, through k1, k2). each of them is connected in series with a 50 Ohm resistors. the voltage source is 64.3V-amplitude 2MHz sine wave. the simulation result of V_L0, V_L1, V_L2 are shown in (...)

## Phase noise (rad and dBc/Hz)

What is the difference between phase noise in rad and dBc/Hz. I would like to know how to convert radians into dBc/Hz. thanks in advance :)

## Fitting a cole-cole model to data

there is an article on the website the Designer's guide Community - A Resource for Analog, RF, and Mixed-Signal Circuit designers by Ken Kundert entitled 'Modeling dielectric absorption in capacitors' that may be of use. It includes a number of references. Guessing from the nature of your (...)

## Matlab: How to get the PSD of a signal?

See the Designer's guide Community Forum - how to estimate the PSD of a complex signal in MATLAB

## Sampled Mode of PAC or PXF in Cadence Spectre

Sampled Mode exists in PAC and PXF of Cadence Spectre. This mode is similar to "timedomain" mode in Pnoise Analysis of Cadence Spectre. the Designer's guide Community Forum - switched capacitor integrator noise simulation results However I can't get reasonable results for

## Scatter plot of montecarlo simualtion results

Hi When I plot the montecarlo simulation result using scatter plot three parameter are shown on the figure (r, m and b) Can anyone tell me what are these parameters? ( I have attaced the scatter plot results) Thanks for your help :)

I don't know spectrum() function in DFII 5.1.41. But it seems that there is no difference between spectrum() function and dft() function. By the way, new waveform viewer, ViVA provide function sets for evaluation of ADC. the Designer's guide Community Forum - snr of adc calcu

## phase selector verilog-A model

Use @timer(). @(timer(period/2+phase, period/2)) state= !state; V(vout) <+ V(vdd,vss) * transition(state, 0.0, tr, tf); end Also see the Designer's guide Community Forum - verilog A code for 16:1 mux My cadence

## How to import CST or HFSS result into Cadence Spectre?

Use S-parameter of Touchstone format. the Designer's guide Community Forum - conversion of .s8p into SpectreRF netlist

## plot quality factor and capacitance vs freuqncy curves in cadence spectre

See the followings. the Designer's guide Community Forum - Simulation Setup for Varactor C-V and Q-freq curve the Designer's guide Community Forum - Inductance extraction: L reduce with frequency?

See the Designer's guide Community Forum - Interpretation of Minimal value in LSB-Noise of Crystal Oscillator

## Amplifiers, Back-Off and Modulation, QPSK

See the Designer's guide Community Forum - Two tone test for transmitter / PA

## difference between noise voltage and noise current

See my appends in the Designer's guide Community Forum - RF circuit Dc bias question

## Need help with monte carlo analysis

hello, I am just a beginner in this field. I am trying to learn how to use monte carlo analysis. I created an inverter by using symbol nmos4 and pmos4. then i wrote a .scs file based on mos1. I don't care if the parameter variation(vto) is reasonable. I just want to see the spreading of the output curve. After simulating I (...)

## Verilog-a code for 4x16 decoder

Use "case ~ endcase" statement in Verilog-A code. See the followings. the Designer's guide Community Forum - verilog A code for 16:1 mux

## how to simulate the noise of pfd+cp+lpf using hspicerf ?

I am frankly waiting for your help~~~Do you think there is anyone who can answer with your poor descriptions. This is also very true for the Designer's guide Community Forum - needs your comment: how to take power supply noise into account for PLL d

## Spectre search option

the Designer's guide Community Forum - Spectre search option

## eye diagram aperture measurements

See the followings. the Designer's guide Community Forum - PRBS pattern for eye diagram USB FS driver... the Designer's guide Community Forum - Automation of Eye Aperture Ratio Measurement [url=www.desi

## basic questions in digital layout

Yes Novice, the CAD tools can take care of the algorithms and stuff like that. But each command for a tool will have several options...these options will make a difference how the tool perceives a task. At the end of the day a tool needs to be told what it must do...thats where we (...)

hi there, I just begin to do RF circuit design and I have some very fundamental question to ask, please help me if you know the answer. what is periodic or quasi-periodic steady state of a circuit and what is pss analysis and its difference between transient analysis(or DC analysis?) used in analog circuit design? why are the stimulus (...)

## help on verilog-A VCO

hi I find a statement in Verilog-A VCO, just as: phase_nonlin = `M_TWO_PI * vco_gain * idtmod ( V(vin), 0, 1000.0, 0.0); I don't know why use the function idtmod(), and I cannot understand the meanings about this function in verilogA mannual. who can help me?

## positive pnmx encountered for push-push oscillator in ads

See the followings. the Designer's guide Community Forum - phase noise of ring oscillator using spectre the Designer's guide Community Forum - phase noise of ring oscillator using spectre [url=www

## transient analysis problem

tran.tran.trn "For Spectre writing PSF data: setenv PSF_WRITE_CHUNK_MODE_ON true" You are using SST2 output format. the environment variable only works for PSF output format. See