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Time Delay Circuit Design

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34 Threads found on edaboard.com: Time Delay Circuit Design
help me design circuit zero crossing from picture106747 i want circuit zero crossing but Rise edge and Fall edge from picture this concept for input interrupt of controller and i delay time with zero crossing of sine wave
I have designed a 16-bit modified radix-4 booth multiplier in cadence and simulated it using ADE (Analog design Environment). I wonder if there is any automatic method to calculate the worst case propagation delay of this circuit or I have to use a brute force method to find it? As a matter of fact I don't have enough (...)
Hello all, I'm trying to design a reversible circuit and calculate its area, power and delay on different standard cell libraries (like 135nm, 90n, 65nm, 45nm, 25nm etc). I'm new to Tanner EDA and have seen people doing it. I've gone through different links people have provided time to time but most of (...)
Try to find out which parameter variation(s) (vth ?) mainly affect the propagation delay time - then you can venture for design counter action.
There are many solution : try to check each step by mark LED warnning on you algorihm that call "Stobing Signal" , and you should design circuit for noise also by make delay time for seqence signal.
i want to build a timer circuit ... that can give me a 1minute to 2 hours of delay approximately ...!!!! if any body have any information ... please help me .... i have tried using cd4060 ic and also 4060 b ic but failed to achieve target ...!!!
Hi, I am trying to design a Flip-Flop. I am using Cadence Virtuoso. I am trying to get the setup time of the circuit by checking the point where the c-q delay increases by 20%. Can you help me with varying the position of rising edge of data with respect to the clock. I also think that I might have to use PERL script to (...)
Consider a totem pole driven Class D and another one with out totem pole drive and ponder the following questions in my mind 1.Which of the two will have higher response time ? This is my take in it The one with a totem pols drive has a higher levels of BJT so it will have higher response time 2. For a high speed response ckt what (...)
Besides pin diodes, 50 ohm matched coaxial relays would promise the best performance. It's definitely the standard solution in test and measurement applications, if switching time isn't critical. Otherwise, you should also look for GaAs analog switches.
You can use a mmic phase shifter chip, such as The trick will be to find one off-the-shelf for your 1-2 ghz frequency band. You can design your own phase shifer, using time delay length of microstrip line that get switched in/out. The benefit of this approach is that you can
Hi, I'd like to design a circuit such that at first, the circuit is completely powered off. The user pushes a switch, which injects power into the circuit. Then a mechanism maintains the power active, even if the switch has been released. At a later about 3 seconds, when the circuit does no longer need (...)
The bandgap doesn't need to settle at Vdd's time. You can never guarantee that if Vdd is being applied externally. That is why I am suggesting to create a bgok signal. Vdd comes up but since the bgok signal is not there the output of the POR block will be still high since the bgok signal is holding it that way. Only when the bgok signal comes then
It is easy,you have make some circuit of zero crossing externally.this signal feed one of microcontroller port bit. and from that point to start delay. one half sine wave of 50 hz has a time of 20 milli sec. if trigger pulse delayed for say 10 mili sec. after this time produce a sharp pulse say 100 u-sec. (...)
i have successfully synthesised and stimulated a design in xilinx ise. now i need to find the power area and delay for the circuit using the tool only.....can somebody provide me with any material to help with it or any hints at how to do it... thank you in advance for your time.. plz help....
I believe you can build a comb logic to monitor the input every 1ns and have a counter running. If for 5 consecutive sampling if the input is sensed as HIGH then the output should be driven HIGH for 5ns and reset the counter. Otherwise the output should be driven LOW and reset the counter. Obviously the method I described above has a delay of 5
Hi all I am quite new to ASIC design. This time I want to design a circuit to delay for a certain time, such as 3us. I would like to use inverters and capacitors. My current ideas is just tweak the L and W and the value of the capacitor. And maybe using two stages are better (easy to (...)
Hi dear all friends, i have to use of None-Overlapping Clock Generator(NOCG) in my project.although NOCG circuit is so simple but i don't know how can design this circuit. is it possible to find size of transistors theoretically or we must find sizes with time consuming trial and error procedure? i spent to many (...)
Hi, i will plan to design the remote switch board with timer control with mc.i need the ir remote ckt . how to create time delay in pic18F252.anybody help me give some ideas.252
Hi, Use a comparator driven relay, which is switched off when voltage is above 40V. Hope the relay off time delay is OK for your application? Regards, Laktronics
Dear all, I need a 10ms delay time. Is it possible to design a delay circuit by using schmitt trigger?
delay time <10ns Thanks
there is a digital input signal to control the turn on/off state of the chip. SPEC of the control input circuit: power supply +5V logical Input high voltage 1.5V (min) logital Input low voltage 0.6V (max) delay time <10ns (best <5ns) a conventional Schmitt (...)
Hi friends, I'm current doing a project on the above topic. I need help in the beamforming simulation. And also in the circuit design. I'm using LSB-WB Ampitude Modulation for the signal processing part. I would require an Amplifier, low pass filter, adder, time delay, shading (for width control) and power amplifier(to (...)
If you have no limitations on the output duty cycle, then you can do the following : apply the input signal (with period T ) to delay line (or a buffer) whose delay is adjusted to (T/4) , then XOR the input signal with the delayed one .. but take care , this circuit doesn't work all the time.
The propagation delay of the cell is related to the rise and fall time of the cell by this: Tp = (Trise+Tfall)/2
1.Driver output rising time/falling time 2.Propagation delay
Try this circuit. The 1st opamp, transistor and resistor act as a current source and creates a ramp on the capacitor. The second opamp just acts as a comparator. The current is (Vcc-Vref)/R1. time = C1*Vref/I = Vref*R1*C1/(Vcc-Vref) so you can set R1 and C1 to get time=1sec
the simplest method is to use a RC delay + an inverter to design POR circuit, and you can search on google for how to design the power on reset. if you need more time, you can also used a timer to assign enough time for POR.
Full gatelevelsimulation with SDF is time consuming when the design is large ,formal verication is a better choice!
it is not possible to get 1/3 without passives or some sort of pll or duty measurement. Because it is not possible to manage rise or fall time without processing of full signal period. Of course you can design a delay circuit . It is matter of things which deserves those efforts . But you can get 1/3 duty for twice lower (...)
u can increase the delay time by increasing the load capacitance .
kokikak2, You may need to design a all pass filter for this application. delay time will be a constant but shifted phase will be depand on frequency. No matter you design a circuit to shift phase of tone. But it's nearly improsible to shift a board band analog signal in a same vaule of phase. (...)
I think you can do like this: Use LM555 IC to create a Pulse wave which has duty cycle and frequency belong to your adjustment. Use this Pusle to charge a capacitor through a resistor. Use a comparator to verify the voltage threshold on a pole of capacitor and turnup your circuit's stage. delay time can change by change the duty cycle and (...)
Is this command used to report the min hold time of the circuit? If so, according to the dc report, the min hold time=data required time in the report=clock uncertainty + output external delay + ... Why the output external delay is part of the min hold time?