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95 Threads found on edaboard.com: Timing Controller
Dear All My Friends I have a decorative light RGB leds it's have an IC SM16726 to Drive i need to control it with pic micro controller .... i face a two problems 1- the datasheet is chines language ... and i can't understand chines 2- the ACROBAT reader can't display the chines language pdf then i can't even see the timing diagram to understand
Hi, I strongly recommend to use interrupt controlled regulation loop. This ensures a fixed timing. Fixed timing is essential for filters, PID control loops. Only with fixed timing you can calculate dead_time, delay time, phase angle .... Additionally you gain a lot of processing power for other tasks. Klaus
i think that is because the data will transfer in two direction , for the MCLK is comes from controller ,if you used the MCLK to sample the data output from DDR you will have some trouble in sync between data and clk,it easier to control the timing when using the DQS come out from memory together with data signals.
What's next? Drill a hole into the chip and observe which memory cells are still working? Your test description is a bit vague, but you probably didn't consider the complexity of DDR RAM operation. After power on reset, the RAM controller performs a timing calibration sequence, writing and reading arbitrary data. With your intentional data line
Hi everybody, I'm looking for a solution for my controller which has its central unit and/or displays out of work. I'm going to upload a photo of this controller where you can see the "operational area" (at the end of which various wires must be connected). There, nearly 13V arrive (in a track where I drew a left pointing arrow in red), crossin
I haven't use this controller. But many compilers support examples (simple in many cases) for various microcontroller families. Sometimes this is better, because you directly run a project and have some fun by changing the timing of a flashing LED etc. Just make sure to select the proper emulator from the project settings. If you are a (...)
I am aware that when designing SDRAM controllers, it is important to not just be aware of how the SDRAM works but also be careful about the tight timing requirements. Now with emphasis on this second aspect, how would one go about verifying an SDRAM controller design written in a HDL? Do manufacturers of SDRAMs provide some sort of (...)
hi, If I want to do static timing analysis of my design having MBIST controller I need to consider the whole MBIST circuitry for STA or only those parts of MBIST where my functional path goes through ?? In case of MBIST only MBIST collar will come in design functional path so according to me only MBIST collar has to be considered for doing STA ?
Hi I am interested to know the details and technicalities of a automated memory controller phase tuning. As the EMMC/DDR memory gains in speed, the timing constraints and Signal Integrity become more and more important and critical. I have got some information from JEDEC but the details are not clear on how memory controllers in a (...)
Well that is at least progress in the right direction. I still believe there could be a timing issue, which might account for the change when you switched compiler versions. I still waiting for a friend of mine to get back with me on his experiences with this controller. I let you know if he has anything to share. Ciao[/
The C language has no timing statements. You are talking about compiler and processor specific library functions or time related functions of an operation system.
Hello, everybody! I have some misunderstanding about VIH(ac)\VIL(ac) SSTL levels. timing specification for DDR3-1066 SDRAM normalized by this levels, for example data setup time tDS is 25ps@AC175 and 90ps@AC135. Which one of all levels I should use in my timing budget calculation? Levels are determined by configuring the controller? or (...)
Hi, In that condition the micro acts as a simple timing device; exactly how it performs that function is down to the program code you give it. It controls the led by turning one of its output ports high or low which allows the current to flow, via a current limiting resistor, to the led. There are many tutorials / books out there to give you
Should be discussed with meaningful code examples. I didn't use bit-bang mode with high-speed chips yet, but generally, I would assume that the timing is accurate within a single bit-bang sequence packet send to the controller.
1.Does the length of the can wires affect any calculation for bit timing? 2.Can any wires be used for can high & low? 3.How do you calculate the propagation delay?,In the mcp2515 datasheet the values are assumed and no formula is given for the calculation.
Hi, I am using Xilinx's "video timing controller ip" for my image processing pipeline/design. I have downloaded hardware evaluation license for the ip. I have implemented this along with other ip's. I am facing following issue 1) I am feeding input to this ip, but it's out is always 0. 2) To check whether this ip is alive, I tried to a
The problem refers to the timing of lcd functions which aren't shown in your post.
The core should have a ucf (constraint) file that has timing, io placement, and io standards. Did you include it in the project?
battery is 4.22 Volts dropping to 3.9 in 4.0Min: Motor Amp Draw is 2.0 - 3.0 Amps , On Resistance is between .0004 and .0003 The Speed controller has a built in timing advance ...: Your motor draws over 12 Watts while the controller loses I^2*R=3^2*0.0004 =0.0036 Watts, so there is no loss to gai
for interfacing 24c16 with controller P89V51RD2 then you will need to use I2C protocol but this controller don't have inbuilt this protocol. so, you will need to design your own software I2C protocol. after refering datasheet of EEPROM then on base of timing diagram you can do it.
start by reading carefully the 8257 datasheet try to get a good copy of the datasheet since they were all scanned from old books, or old copies. try to undersatnd exactly the functionallity of the part what are inputs and outputs, and were the are connected to. what the timing relashionship between signals. what are the differnt operation m
Have you put the dsub pins on a scope to make sure it looks ok? do they meet the timing and voltage specs?
Hi, I am trying to interface a Cypress sl811hst-axc usb host / slave controller with an Altera Cyclone I FPGA, the cyperss chip isn't responding to my signals, I've tried to write an 8bit data to a random address of the chip by driving the controls lines, corresponding to the timing diagram provided with the chip datasheet, and then read at the sam
Not in ISE use EDK to add NOR flash controller and after adding the controller change the timing parameters based on your device..
If you have the command order and a timing diagram for the bus, it should be fairly straight forward. You just write some controller for the chip and away you go. If you dont know where to start, I suggest a book on digital logic design and a VHDL tutorial.
Dear All, I am using PIC 16F676 controller for my project. I am using this controller to control the relay. As per the program the relay must be closed at 1.30 mins(90 seconds) but it starts to work from 1.19 mins itself. How can I match this timing. Kindly help me to solve this problem.
is this correct????? does it affect timing of fetching data?? is there any other ways to combine this two without wasting time?? im using a AC POWER ANALYZER that transmits data every second. PIC16f4550 is my controller... while(1) { while(1) { do{ dat = Soft_Uart_Read(&err); }while(err); if(dat =
Hi friends I need to measure the serial communication speed in PIC16f877A Ic.How to calculate timing between PC and microcontroller? How to increase SPEED between PC to MC? Am used Asynchronous serial communication. How to rectify this problem?
Can anyone give me any idea that how can I generate two pulses with 90° phase shift with pic micro-controller? The frequency is 50Hz, and I've to show 4 different data in LCD too with this operation. As I did a rough where I can't get the exact timing. It creates a delay for LCD and ADCRead. how can I generate these continuous pulses without harmin
I am using DS1307 in my project for timing ... DS1307 has got a backup battery which runs the time when we has switched of the controller. . . but the problem is that when i turn off the power of DS1307 it stops and does not measure the time....And when i switch on the controller again .. it resumes form the time where i switched it (...)
Where do you get the timing information for the DDR2 controller implemented using MIG?
VGA has data and timing signals. have a look here: Video Graphics Array - Wikipedia, the free encyclopedia
LCD Initialization needs proper timing. I cant see delay between the commands. Refer LCD datasheet for proper timings.
scd, Your question doesnot give us any details. Are you trying to interface it to some controller? Is your hardware tested Are you having issues with software Have you tested each thermal printer parts Were you able to run only motor first Are you following correct timing sequence Are you providing appropriate power input Weather it is battery po
Hi to all .I try for two months to make ad work .I just use my spi controller . My vhdl script is exactly as timing diagrams chapter 9, ug334 . Is there anything that is not metioned in manual that creates problems such as desabling other spi is not mentioned . i change spi_sck frequency and have different results. why? i just tried to
You have LCD problems? LCd timing are 100% ok? Are you change lcd? have you power lines/wires and maybe high speed change of long wires? Noise in environment?
Now, for my IC module, i do not have any timer left available. Yes, obviously. You can either go for software PWM generation or software event capture, depending on your required timing accuracy. Or use a processor with more independant working timers, e.g. a dsPIC33 motor controller.
Hi, Try to follow this 1. check wheter clk period of the model is within the range u r operating 2. Check whethet, the ddr2 model attached supports all the fetaures enabled in MIG 3. Check the initiationlation, in ddr2 model you should see init done indication 4. All the timing paramemter -shyam
Hi folks, I need I2C and I2S protocol checkers (which is available without any company confidentiality). If anybody uses such open source code please share the same. More interested in modelling the "timing" models of the I2C Master/Slave models as well as checkers. -paulki
Generally, TrickyDicky is right about the necessicity to register asynchronous inputs to a state machine (or other synchronous logic). Ignoring this requirement is one of the most favourite methods to cause occasional failure of a design. In the present case, db_in(7) is effectively copied to a single register if db_in(7) = '0' then check
Hello to everyone, I'm new in the forums. I'm designing a 10kW BLDC controller for my electric scooter conversion. Currently I'm using BLDC motor with hall sensors on all three phases, but there are problems with timing - the sensors are not ideally aligned and I get a timing error that produces 1kW of waste energy. So now I'm going for (...)
have you refered the SPI specification before writing the driver? Does your driver follows the timing requited by SPI standard and also required for the memory? You can verify this first using DSO, before checking memory write and read. One this is clear. Then check for the wave form details for write and read cycle in memory data sheet. and ver
Hi Every body, I am using MSP430F5435A to interface with SAP3305 LCD controller. I could not able to light up the LCD, Coud any one help me to see my code and correct. I am not sure it is because of timing issue. The SAP3305 controller and RA8835 are same. the code is bellow, #include #include "SAP3305.h" #define (...)
BRAM is just standard Xilinx Block RAM. Look at the the Xilinx datasheet for BRAM to get an idea of the timing diagrams for reading and writing. Then write an RTL module that takes the serial SPI data and then writes it to the BRAM as parallel data.
hi i've generate a DDR3 memory controller from altera and i would like to know is this memory controller consider the timing according to the JEDEC ddr3 spec? and is there any universal memory controller for all type of ddr available in the market? thanks.
Hello Everyone, I have got a bunch of questions for the fpga experts out here. I am trying to create a design in fpga using softcore MAC controller and MCB on spartan6 device. All the timing constraints are met in post-place and route but still i see the firmware crashing some times. I didnot perform timing simulation? Is it (...)
The enable signal should be high & low according to the timing ONCE when valid data comes/changes. But my enable is changing multiple times during the same data. How can I write the logic so that the enable process is NOT repeated for valid data more than once? For subsequent valid data Enable should again be high & low once.
Connect all the digital signals on the DAC to the FPGA and the write an FPGA controller to send the data based on the timing of the DAC and you will see the proper signal coming out. The issue with the AD9706 is that you need to change the setting of the DAC via SPI, you can do that either by adding a SPI controller to your FPGA and let (...)
what do you want to test? 1. sensitivity -- you need simulator 2. timing -- PPS (pulse per second), coneect it to a oscilator or a timing source to measure accuracy. 3. CEP -- log position data. .... Hpoe this helps in deciding, BRM
Hi all, I'm working on AES implemtation in FPGA. I need to send Encrypted data's to DSP (or FFT/IFFT) through SPI port. I have written SPI controller module in verilog. I want to know to how to calculate Set-up / Hold time to interface with DSP board SPI peripherals.?. On What basis we have to write timing Constraints ? Kindly help me. Th


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