15 Threads found on edaboard.com: Toggle Coverage
A truly VLSI circuit is going to be a bear to simulate in any SPICE.
That's a lot of nodes. And if you want every gate in it to toggle
at some point in an application-realistic worst case sort of way,
that could be a whole lot of test vectors. Figuring about one
vector per gate being a rough norm for a full coverage test
pattern, clock period, do t
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-20-2016 13:03 :: dick_freebird :: Replies: 3 :: Views: 406
The IDDQ target is to cover maximum no of states for each logic gate in given design. we no need to observe any fault outside.
Hence is just a toggle profile. due to these reasons the IDDQ coverage is high with lesser patterns.
ASIC Design Methodologies and Tools (Digital) :: 01-24-2013 01:47 :: rameshsuthapalli :: Replies: 2 :: Views: 635
I want to exclude bits in toggle coverage. I m working on cadence (iccr) tool.
I used this "set_toggle_excludefile" command in coverage configuration file has .ccf extension.
I created two file one exclude_bits.ccf and other one is exclude_file.dat.
contents of exclude_file.dat. file:
-ere instance (...)
ASIC Design Methodologies and Tools (Digital) :: 04-19-2012 06:56 :: smart.shivani11 :: Replies: 0 :: Views: 1088
yes,you can't say verification is completed for design and you can say only that i have done verification of some percentage(%)...
the percentages based on your verification strategies. like if you done branch coverage you can say how many branches have you exercised successfully, if you done toggle coverage you can say how much % of (...)
ASIC Design Methodologies and Tools (Digital) :: 11-01-2011 05:11 :: sathi.repala :: Replies: 1 :: Views: 757
My design run with VCS 7.0 report toggle rate is 0. The cm.log message is following :
Starting toggle coverage for module RM5012_SIM_TOP.RM5012.TOP.RM5012_TOP_ROM
: Starting toggle coverage for module RM5012_SIM_TOP.RM5012.TOP.RM5012_TOP_ROM.u_dafilter_top
: Starting toggle (...)
ASIC Design Methodologies and Tools (Digital) :: 09-11-2009 06:09 :: wartwo :: Replies: 4 :: Views: 1453
What's the Significance of toggle coverage in Code coverage.
Why we need toggle coverage. What's the use of this and Where is the application.
ASIC Design Methodologies and Tools (Digital) :: 08-15-2009 23:12 :: spartanthewarrior :: Replies: 3 :: Views: 3405
I am just wondering, do we need to run the code coverage at the gate-level netlist?
Can the code coverage from cadence support code coverage at the gate-level netlist? Thanks
To a limited extent yes. For instance:
* toggle cov on important nets
* FSM coming out of reset properly
ASIC Design Methodologies and Tools (Digital) :: 07-22-2008 11:16 :: aji_vlsi :: Replies: 7 :: Views: 1455
While generating patterns for transition faults, should the reset be declared as a clock or not?
How does declaring the reset as clock help in increasing test coverage for transition patterns when it is known that the reset cannot toggle at speed? Will such patterns pass in the tester?
ASIC Design Methodologies and Tools (Digital) :: 03-02-2008 06:37 :: anjana_das :: Replies: 2 :: Views: 927
I am trying to generate severate coverage reports and merge them after that. This error appear when I merge it and produce a report. I have no idea what it means and I am notsure whether the coverage report generated actually reflects the true result.
What I did was:
vlog -cover bst -f ../files.vc;
vsim -c -coverage tbench -do (...)
Software Problems, Hints and Reviews :: 06-21-2007 05:37 :: khorlipmin :: Replies: 0 :: Views: 1552
Firstly, u need to compile ur design file with ur selected coverage. For example,
ModelSim > vlog -cover bcst file_name.v
Here, ur coverage are b=branch, c=condition, s=statement and t=toggle.
ModelSim > vsim -coverage file_testbench.v
next, run -all.
OR, u can enable it using GUI. U go to (...)
ASIC Design Methodologies and Tools (Digital) :: 02-26-2007 04:01 :: no_mad :: Replies: 8 :: Views: 17529
The coverage have two .the first is code coverage, if you use some coverage tools , you should see such as:
condition coverage , code coverage , brach coverage, toggle coverage and more. when you verify , you should reach 100% of those, the tools manual (...)
ASIC Design Methodologies and Tools (Digital) :: 08-08-2005 11:11 :: xworld2008 :: Replies: 16 :: Views: 1267
I was try to get good toggle coverage for my design!!!
Here were some reports from VCS
// Net coverage
// Name toggled 1->0 0->1
ASIC Design Methodologies and Tools (Digital) :: 11-29-2004 04:21 :: etrobin :: Replies: 1 :: Views: 1649
Modelsim also provide code coverage covering statements, branch, expression and toggle coverage. I find it quite user friendly, just need to compile with the coverage options that you want and then simulate by turning on coverage, interactively or script driven.
ASIC Design Methodologies and Tools (Digital) :: 11-09-2004 10:28 :: jkfoo :: Replies: 8 :: Views: 1773
Verilog code-coverage utility
Covered is a Verilog code-coverage utility used for Design Verification which is capable of performing line, toggle, combinational logic and finite state machine (FSM) coverage analysis.
2. -> t
Software Links :: 04-03-2003 08:45 :: jimjim2k :: Replies: 0 :: Views: 625
1. use design compiler's utility vcd2saif to generate the switch activity information and read into test compiler to report the coverage info.
2. there is one toggle rate caculate PLI example under nc-sim's sub-directory , compiled it then use PLI link from simulator to get the result .
ASIC Design Methodologies and Tools (Digital) :: 01-22-2003 16:19 :: Nobody :: Replies: 3 :: Views: 2942