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Transistor Sizing Logic

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4 Threads found on edaboard.com: Transistor Sizing Logic
9927199272 friends..i'ma beginner to cadence.. last day i tried to implement pose edge d flip flop using transistors(logic gates). Now i'm facing a problem.The circuit is passing data line on both edge of the clock. Can anybody help me to figure out what went wrong with this circuit design
please anybody tell me... Is it required transistor sizing when phase detector designing...iam not getting output at the PFD(iam using 0.18um cadence)...
The transistor parameter most useful is beta. You need enough base current so that beta times this flows in the collector and the collector resistor is large enough to drop all of Vcc at this collector current. Then to increase switching speed you need to go beyond this and have a "over drive" effect by sizing the resistors so that there is an
Hi friends, I want to learn how to size my inverter (or a nand gate) for a fan out of 4. i.e my gate has to drive 4 similar gates. I know how to size the transistors of a given gate for equal drive capability(i.e equal drive of pull up and pull down networks). Please help me in this regard. Thanks,