18 Threads found on edaboard.com: Trigger Chipscope
RAM is used to store captured data. You define condition which will be used as a trigger for internal data capturing in real-time. After that you can download this data from FPGA through JTAG to analyse in PC. CPLD has no memory (just limited number of FFs), so there is no place to store captured data.
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.02.2005 12:54 :: Ace-X :: Replies: 13 :: Views: 2254
Now I want to see the internal signal in the fpga under test,so I use the chipscope but The chipscope does'nt work correctly,sometimes it can trigger however the match function I use.and the datas are always 0s,sometimes it can't trigger however the match function I use,and it displays waiting for trigger.I (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.04.2005 22:54 :: bjzhangwn :: Replies: 10 :: Views: 1417
I have some problems about chipscope 8.1i, please help me.
I want to capture the address and data in a ram. And i expect the adress increase one by one,but the result is not as i expect,the capture address is disorder. I want to know why? and in the trigger setup there are WINDOW and N SAMPLES setting. i don't know much abot it
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.07.2006 12:50 :: wowuyou :: Replies: 1 :: Views: 768
I have a simple VHDL counter modul that I wanna debug with chipscope 7.1 on a Virtex II board:
entity top is
clk : in std_logic := ?0?;
cnt : out std_logic_vector(3 downto 0)
architecture behave of top is
signal counter :
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.01.2008 15:06 :: grubby23 :: Replies: 1 :: Views: 1136
In fact the chipscope only makes state analysis!
When you are using the CLK signal for trigger/clock you can't see it!
You must have an additional signal with higher frequency (for example x2 or more) and this signal is use for the chipscope trigger/clock, now u can see your CLK signal.
For this you can (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.01.2008 12:31 :: tomasulo :: Replies: 4 :: Views: 1302
Hi, I am using chipscope analyzer. after the trigger signal it shows the buffer has some data. but it is not full. Then I select Stop button. but It does not show buffered data. Is there anything I do not take into account?
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.03.2008 11:42 :: ehsan_iut :: Replies: 5 :: Views: 812
I could get rid of the above problem by changing the clock not the trigger condition but It seems that i have to use the output of DCM(digital clock mananger) as clocking signal in chipscope . Please let me know whether i am going in a right way or not
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.07.2008 23:03 :: kalyansrinivas :: Replies: 3 :: Views: 2954
Hello guys, I'M using chipscope pro 8.2 version. I have monitored the pin or buffer inside FPGA by assigning the ports and triggers and clks. Now when running "Analyse using chipscope", I can read the data from the desired registers as a time basis, that is I can only view a few set of samples (512 or 1024 upto 16384) which were selectable (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.11.2008 03:43 :: xtcx :: Replies: 0 :: Views: 546
Just add reset signal, and give trigger on that, then press reset button, if in this case also same problem comes then your clock is not running. Make some counter which runs on clock (used by chipscopro) and assign 27th bit to led available on your board and varify.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.03.2010 06:38 :: shitansh :: Replies: 5 :: Views: 909
You need not provide the pin number information while inserting the core.
Insert the signals u need to tap, trigger, sampling clock, depth... compile the design again and then analyse thru chipscope analyser. Pls check the appropriate manual...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.04.2010 06:26 :: param :: Replies: 2 :: Views: 820
I would like to know the function of the chipscope ILA trigger and how to use it ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.06.2010 10:57 :: omara007 :: Replies: 5 :: Views: 1519
I have a problem with setting up the input data onto chipscope debugger.
Say, I want to implement a simple 1 bit adder :
entity CLA_1bit is
Port ( A : in std_logic ;
B : in std_logic ;
C : in std_logic ;
S : out std_logic ;
P : out std_logic ;
G : out std_logic) ;
architecture Behavioral of CLA_
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.08.2010 06:04 :: satishgra :: Replies: 3 :: Views: 1130
I'm using MIG as DDR2 controller in virtex5.
I created a cdc file for using chipscope. But while using the pins to trigger, only one bit of some registers appears in the list, but I need to trigger all (128 or 64) bits of the register. i don't know what the problem is.
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.05.2011 06:31 :: hastidot :: Replies: 1 :: Views: 374
1) What is the maximum speed at which we can watch Flip-flop value changing through chipscope ?
I'd say it is directly proportional to your flipflop clock. If you use 300MHz clock, you can watch flipflop value changing at 300MHz rate. No doubt.
But remember, that this is true only for synchronous designs.
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.01.2012 05:48 :: xtcx :: Replies: 11 :: Views: 1013
Using trigger in chipscope, can I make multiple triggers, and every run, choosing just one of them to be the active trigger, while disabling the others?
This way I don't need to compile all design when I want to change triggers.
Can it be done?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.02.2012 07:37 :: yuvalkesi :: Replies: 2 :: Views: 426
Can we have two clocks for trigger signals to be monitored on chipscope?
What is the way to monitor multirate data with chipscope? I have a design with an output signal with high decimation (>1000). I want to monitor both the high sample rate signal as well as the decimated signal. Is there any way out as we can add only 1 .cdc into a project.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.03.2012 05:11 :: ravics :: Replies: 1 :: Views: 343
Thanks for your info. I went thruw that website. i could not understand wht does it mean by one needs to set trigger. how can i just monitor the internal buses while the fpga is interacting with software thru PCI.
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.08.2006 00:45 :: s3034585 :: Replies: 14 :: Views: 1269
There is a big problem with determining the cause very strange bug:
Project in the crystal Xilinx works fine, but from only 7-10 hours and then one part of it hangs.
Now the details: By many experiments revealed that error inside the trigger of Xilinx chip (ie the output signal ceases to be):
start_flag <= (((EQUAL (rxd_sync (63 downto 56), SF
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.10.2010 15:06 :: asjohnas :: Replies: 3 :: Views: 482