65 Threads found on edaboard.com: Triple Gate
Hi, all,
What are the difference between (0.18um)high-voltage triple gate process and other process (typicallly used in mixed signal circuits)? I have seen dual gate process so that we can double the supply voltage so that we can have higher output swing...and so on...
I understand that thicker gate process endures (...)
Analog Circuit Design :: 19.06.2006 23:49 :: ee484 :: Replies: 0 :: Views: 393
Hi gurus,
Am new to this groups and novice in hardware stuff.
I found that
If (in protected mode) A20 gate is used to access odd megabytes.
and is used to reset the cpu so that we can go back to real mode from protected mode.
In another article i read that triple faulting also used to reset the cpu.
1. if present day OS boots at prote
Microcontrollers :: 21.09.2006 14:51 :: sureshkumarp :: Replies: 0 :: Views: 333
We need to know the range of voltages you are trying to pass.
If it includes the negative range, are you sure that your process has triple well capabilities to support it?
Analog Circuit Design :: 07.03.2011 12:25 :: checkmate :: Replies: 5 :: Views: 1682
Dear all,
I 'm doing standard cell of library.
Different gates have different gate sizing that will satisfy systhsis request.
For all types of driving strength in standard cell, I 'm no idea how to decide the Normal(1X) condition.
e.g.
----------------------------------------------------------------------------------------
Driving S
ASIC Design Methodologies and Tools (Digital) :: 03.01.2008 09:43 :: rain_181914 :: Replies: 16 :: Views: 1856
basically the substrate isolation. triple well transistors are more isolated.
khouly
Analog IC Design and Layout :: 12.11.2008 10:43 :: khouly :: Replies: 9 :: Views: 11685
i mean like(strained silicon) (triple gate mos) finfet) ....etc
Analog IC Design and Layout :: 27.11.2008 22:49 :: THUNDERRr :: Replies: 6 :: Views: 974
Hi everyone,
We are using IBM 65nm cmos10lpe process.
Our design used a triple-well RF nfet (nfettw_rf). However, when we checked DRC with Calibre, the tool generated the following result:
"triple well tie-down rule: must touch RX, which is electrically connected to (RX over NW) through M1"
Could you plea
Analog Circuit Design :: 19.10.2009 05:22 :: chickenvlsi :: Replies: 1 :: Views: 1684
Hi... Has anyone has worked on TAB full bridge DC DC converter where power can be transferred from one port to another port by changing the phase shift of the square wave pulse to the switches of the bridge.
I did a simulation but I obtained that power is transferred even when gate pulse sent to all the switches of the bridges are in phase.
C
Power Electronics :: 19.03.2010 00:34 :: mess123 :: Replies: 0 :: Views: 596
@ SIMBOX :
Have you any further info about this “glass " filter?
@ Humungus:
- Yes, short channel CMOS give ft's as large as you said allowing working at very high frequency which is quit good for chip area, as L's & C's get smaller, but make it very bad in trying to isolate devices , either using rings or triple wells or any other meth
RF, Microwave, Antennas and Optics :: 28.12.2002 12:18 :: superluminal :: Replies: 18 :: Views: 2473
hi i think that if you need to have a secure bitstream virtex II is betther.
he have a triple des core encription that is a good resource.
bye
G.
Professional Hardware and Electronics Design :: 17.01.2003 15:22 :: tlp71@hotmail.com :: Replies: 15 :: Views: 2893
Is the DRC rule : Metal3 overlapping with VIA2 necessary. What will happen if there is a VIA2 but no Metal3 on top of it in a triple metal layer process. Any potential problem will arise as a result of this?
Even though no physical or electrical problems, leaving VIA2 uncovered by Metal3 is not a good design, because thos
Analog IC Design and Layout :: 08.05.2004 07:31 :: Hughes :: Replies: 12 :: Views: 1351
And here's my pennys worth..
How about a triple layer PCB, and a cheap PIC (protected 508-9?) mcu as the dummy chip, or even better, replace your logic gating circuitry with protected pic software.
Forgot to mention that in some cases copying the design isn't the bigest problem, but the concept (idea) itself, and there isn't much you can do
Professional Hardware and Electronics Design :: 02.10.2004 15:06 :: sda :: Replies: 12 :: Views: 1775
Hi
What is the meaning of N-well Nmos? To my common sense, there will normally be Pmos in N-well. Even if it is triple well, it is actuall still so.
Please correct me if I am wrong. Thanks.
regards,
jordan76
Normally mosfet in nwell is p-type. But we still make nmos in nwell using n+ type S/D implantation.
Analog IC Design and Layout :: 12.10.2004 15:36 :: Hughes :: Replies: 16 :: Views: 1541
triple well means you have a deep Nwell.
Inside the deep N well, you can bias the bulk, which is P well.
Analog IC Design and Layout :: 29.10.2004 05:07 :: mike_bihan :: Replies: 10 :: Views: 2107
To add to Humungus's post,
On the other hand, short channel effects are easier to control in SOI than in bulk.
This statement is only partially true.
For FD SOI, it is easier to control short-channel effects than in bulk silicon. But there are double well and even triple well bulk silicon, which is used to counter such effec
Analog IC Design and Layout :: 27.08.2005 07:01 :: SkyHigh :: Replies: 22 :: Views: 1630
I need to use a 74LS138 de-multiplexer and a single 74LS10 (triple three-input NAND) to implement the folowing boolean function:
F(a, b, c) = abc? + ab? + a?b?c
= abc? + ab?c + ab?c? + a?b?c
Sum of min-terms = (1, 4, 5, 6)
I just don't get how exactly to use 3 3-input NAND gates for 4 outputs.
I thought of connecting the 4 inputs t
Hobby Circuits and Small Projects Problems :: 03.03.2005 10:10 :: solus :: Replies: 4 :: Views: 2246
first - 200uV is exceptional! you can only hope that your chip has less than a few mV of ripple. try to look at it in terms of percent, and keep the percent lower than 1%... or 0.1% for extremely high accuracy.
say your full scale voltage in lock is 0.5v, you can endure 5mV steady state ripple before you reach the 1% region. and if your f
Analog Circuit Design :: 14.06.2005 07:55 :: electronrancher :: Replies: 12 :: Views: 3274
HI
The digital and analog blocks can be separated by TRENCH(triple WELL ISOLATION,DEEP N-WELL Etc),If ur process permits.
If ur process not permits any of the above,U can use N-WELL RING with more than 4 times the minimum width followed by P-type Guard ring.
The digital signal crossings over the analog signals must be SHIELDED.
Guardri
Analog IC Design and Layout :: 11.01.2006 12:42 :: mahendra :: Replies: 7 :: Views: 1199
I have questions about the twin well process in 0.18um.
1. if it is really twin well process, then we can never faced the body effect problem of NMOS, if we always connect body to source, right? Of course, this will increase the area required .
You need triple-well process to be do this. Twin well one has just Nwell and
Analog IC Design and Layout :: 26.11.2005 16:43 :: steer :: Replies: 1 :: Views: 816
I built a pulsed power supply a few years ago for Plasma Ion Implantation.
The pulses were 60kV at about 1400 Amps. The leads to the plasma chamber
were 20 parallel conductors, triple 0 gauge. The leads were about ten feet
long, and suspended above the floor.
The system rep rate was 16 PPS, and the cables danced around like a snake
having
Electronic Elementary Questions :: 15.01.2006 02:10 :: GonzoEngineer :: Replies: 13 :: Views: 1580
I think you should build a PG1 Dongle Programmer from olimex It works fine on some PCs, and in some other PCs , it doesn't work.
Added after 5 minutes:
I'm following this topic for some time now (just reading). I made the ICD2 clone from PICS design.
Microcontrollers :: 11.08.2006 08:22 :: wonbinbk :: Replies: 1853 :: Views: 469175
Thx, all.
I have well antenna definition as followed:
Well Antennas
Increased PFET gate leakage currents and reliability time-dependent dielectric breakdown (TDDB) failures were observed in test structures tied to the substrate with an n+ diode. The assumed cause is charging of the n-well with respect to the gate due to large antenna connections
Analog IC Design and Layout :: 29.03.2007 11:15 :: mary96960 :: Replies: 18 :: Views: 6132
Complementary metal?oxide?semiconductor (CMOS) is a major class of integrated circuits. CMOS technology is used in chips such as microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceive
Electronic Elementary Questions :: 22.05.2007 14:00 :: pravin_dwaramwar :: Replies: 12 :: Views: 768
Hi
Regarding the first topic. It's absolutly ok to wire short distances in poly
If you change the layer to another poly or the first metal layer, it's not
sufficient to compare just the specific resistance of the wiring level, always
watch the contact resistance as well. Contacts usually have an unbelievable
bad resistance, so watch out here
Analog IC Design and Layout :: 05.12.2009 18:18 :: baenisch :: Replies: 17 :: Views: 2686
hi
is it a must to use triple well process to pass negative voltage? can we just use pmos device to pass negative voltage?
i know that pmos device is not good at passing negative voltage, but what is the consequence of using it? for example if i use 0.18 um process and try to pass -12V using pmos, what is the passed output voltage?
thanks:)
Analog IC Design and Layout :: 22.10.2007 09:34 :: sastromuni :: Replies: 6 :: Views: 651
Generally speaking, If you are using a kit you will find a standard cell for your transistor ready to be used..
If you are making own layout, then here are the steps:
1. First draw the well, for NMOS on single well process then no well exists. If PMOS use NWELL, if NMOS on triple well technology use PWELL
2. Then you need to define the OD
Analog IC Design and Layout :: 25.10.2007 10:13 :: aomeen :: Replies: 6 :: Views: 732
For decoupling capacitors for power supply,what it needs is the large capacitance to reject the power supply fluctuation,the capacitor behaves like a reservoir,the larger the capacitance ,the better rejecting the MOS capacitor is prefered for its large capacitance with little area.
the MIM capacitor is more used in Analog and RF circuit
Analog IC Design and Layout :: 03.12.2007 07:57 :: freelancer :: Replies: 9 :: Views: 1400
As a first step you can match the drain/source voltages of the matched PMOS triple. Insert the resistor R3 into the drain of the kT bias loop. That improves up to the point of matching. I guess 20x with reasonable PMOS devices sizes. So please verify with matching! There are other topologies based on NMOS source followers but better would be
Analog Circuit Design :: 10.12.2007 14:14 :: rfsystem :: Replies: 13 :: Views: 1024
Hello all,
I have a signal, of which the integral represents a process variable. (Fig. 1 of references.pdf) I designed a gated integrator (Fig. 2) to isolate the usable portion of the signal. I then sample this output with an ADC and scale appropriately. This works well, however the input signal can be bi-directional (Fig. 3) and the circuit
Analog Circuit Design :: 18.12.2007 19:23 :: keystoneclimber :: Replies: 0 :: Views: 461
Ground bounce is due to rapid current sink/source thru bonding wire between ground pad and package pin. dV= L(dI/dt)
SO the methods to mitigate this ground bouncing effect are:
(1) lower the inductance(L):
for example; double/triple bonding for groung pin. or using flip-chip packaging, ...,etc.
(2) lower the current spike(dI/dt):
for exampl
ASIC Design Methodologies and Tools (Digital) :: 08.03.2008 17:41 :: sunjimmy :: Replies: 7 :: Views: 839
Endcaps are added around the edge of digital core in triple well design, it's used to close the nwell of stdcells to form a ring, which encloses all the digital circuits, what I know is that it's used to speparate the core logic from the outside.
ASIC Design Methodologies and Tools (Digital) :: 17.11.2008 15:42 :: xu_huabing :: Replies: 25 :: Views: 3963
Hello everybody!
I have noticed a strange behavior of the "show incomplete nets" command of virtuoso layout XL.
This command shows that my Vdd_mycel and gnd_mycel nets are not connected, though LVS reports matching! All other nets are shown correctly as connected.
I believe it is not random that the problem is with my power and ground nets of
Software Problems, Hints and Reviews :: 11.11.2008 12:28 :: mixaloybas :: Replies: 1 :: Views: 843
There are a couple ways to make a tripler:
1) antiparallel shottky diodes to generate the 3rd harmonic, and linear amplify after that
2) non-linear element (varactor or step recovery diode) and present the correct impedances/filtering to the element terminals to force it to triple
3) other nonlinear methods, like photonic mach-zender modulators,
RF, Microwave, Antennas and Optics :: 15.04.2009 16:51 :: biff44 :: Replies: 2 :: Views: 617
the top transistor in fig. 1 requires a triple well process to isolate its body from the underlying p-type substrate (body of bottom transistor).
fig.2 can use a simpler process but suffers from body effect.
Analog Circuit Design :: 02.06.2009 14:41 :: ralph007 :: Replies: 3 :: Views: 641
I am looking for a trasistor level circuit which would act as an interface between a 3.3 V supply CMOS logic to 1.2 V CMOS logic circuitry.
Raduga
If the 1.2V transistors can stand a gate-source (and gate-bulk) voltage of 3.3V (resp. -2.1V), you can directly connect the 3.3V logic output to the 1.2V logic input. If not, t
Analog IC Design and Layout :: 27.07.2009 16:30 :: erikl :: Replies: 9 :: Views: 11705
Dear Lynda,
when we use NMOS or PMOS caps, it is desired that they work in a linear region. This happens when they are in accumulation region. Then in normal implantation of them, we should have enough voltage across them to provide accumulation.
In case we make an NMOS in NWELL, there is already accumulation in channel. Then you don't need to
Analog Circuit Design :: 14.08.2009 17:07 :: navidsar :: Replies: 7 :: Views: 2970
Hi ESDSolutions
HHI + MILSCR (Vt1~20V) + triple (quadrupole?) PMOS/NMOS cascodes?
Analog IC Design and Layout :: 30.09.2009 18:17 :: mikersia :: Replies: 9 :: Views: 1004
I agree with you all that if the circuit shown in my 2nd post is used, then the captured encoder signal waveforms much be the same regardless of the rotational direction of the motor.
This morning I checked the hardware (encoder interface board where the 'counter' resides) and found out that the schematic given to me (as shown in my 2nd post) is
Electronic Elementary Questions :: 02.10.2009 02:02 :: powersys :: Replies: 6 :: Views: 1810
At the beginig, device was just a 30V 10A power supply, but when winter comes, I decided to tune up device with rectifier with current regulation.
But let’s start from very beginning
1) power supply is based on well known
Show DIY :: 26.02.2010 09:56 :: gres :: Replies: 0 :: Views: 2062
Not really. A flip flop puts out square waves. If you look at an elementary electronics text book, you will see that a square wave is really made up of sine waves at f, 3f, 5f, 7f...frequency. In other words, the square wave has a lot of energy at the triple of the input frequency, but almost none at the double of the input frequency.
To make
Electronic Elementary Questions :: 26.04.2010 17:30 :: biff44 :: Replies: 1 :: Views: 1821
Hello,
I am trying to use compile_ultra to compile a triple module redundant adder, but the tool keeps optimizing it, transforming in a simple adder. Is there a way to disable such optimizations?
Thanks
ASIC Design Methodologies and Tools (Digital) :: 13.07.2010 22:46 :: rapidshare03 :: Replies: 1 :: Views: 514
I actually don't get what the point of your doubt is. If you dont' have double or triple flopping and the flop is immediately followed by the comb logic that ends up in many flops, the metastable condition would spread out in the logic and a lot of flops down the paths would be unknown state that you want to prevent. Having a double or triple flop
ASIC Design Methodologies and Tools (Digital) :: 06.12.2010 03:13 :: lostinxlation :: Replies: 29 :: Views: 2993
I would suggest the minimum operating voltage would be 12V.
I would really like you to consider operating the off-line section at... at least 80KHz. If you do not then as I say your transformer, and filter inductor, will become large. These sort of frequencies are not uncommon although I might be worried if you are thinking of building this on S-D
Power Electronics :: 23.02.2011 09:49 :: Genomerics :: Replies: 133 :: Views: 7720
I think you could do this if your transistors do not see the full 5.5V input voltage, thus they would need to be in there own wells so you wouldn't break down the transistors. For example if you have diff pair with NMOS inputs you would have to have a triple well process to put those NMos transistors in there own wells. If I remember correctly at
Analog IC Design and Layout :: 30.12.2010 10:15 :: jgk2004 :: Replies: 7 :: Views: 349
Hi again.
Spent a bit of time trying to find a catalogue source for cores in the USA. Not much luck. Perhaps you do have something useful in your parts bin or you might be able to get some 'samples', cough cough.
I've 'massaged' the basic circuit to 'optimise' things. One of the limitations of the previous equation is that it does not account
Power Electronics :: 29.01.2011 10:26 :: Genomerics :: Replies: 23 :: Views: 1953
Hi all,
Maybe something about use of L1 L2 and L3
Mook Johnson wrote:
Gents,
I'm looking at ways to bullet proof a motor driver. I'm using the standard triple half bridge configuration and want to protect against the motor phases shorting to each other or to the case (HV
Power Electronics :: 23.02.2011 18:04 :: jmx66 :: Replies: 2 :: Views: 319
it is safe as long as you double,triple check that only one TRIAC is fired at a time.
or else its going to be a phase SHORT. did you get it?
Electronic Elementary Questions :: 22.02.2011 05:05 :: cameo_2007 :: Replies: 13 :: Views: 389
I am trying to design an op-amp with rail to rail inputs and am finding an issue with the symmetric input stage trick. I am limited to a process with no floating gate and nothing fancy like triple well.
I have tried two approaches, one with a simple dual (symmetric) nmos and pmos differential pair and also with a dual folded cascode approach (se
Analog Circuit Design :: 28.04.2011 18:38 :: phoenixosu :: Replies: 0 :: Views: 407
Bifilar is better (than side by side secondaries - although these do work acceptably well - (TIW - triple insulated wire) and one diode per winding with its own initial cap to keep the loop area down, then paralleling, efficiency is limited by the use of the TOP250 and the forward drop of the output diodes, e.g. for 14.6 vout, a 0.8 volt forward d
Power Electronics :: 10.06.2011 08:33 :: Orson Cart :: Replies: 23 :: Views: 1917
in a triple well process can i short the source and body of a transistor irrespective of wherever it is in the stack right?
Electronic Elementary Questions :: 20.06.2011 23:14 :: chandra3789 :: Replies: 7 :: Views: 538
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90nm cadence | need help for inverter project | transformerless inverter | mosfet boost converter | project file invalid | 8051 temperature sensor | black stick | test simulation library | convert s11 | this program calculates