1000 Threads found on edaboard.com: Triple Gate
What are the difference between (0.18um)high-voltage triple gate process and other process (typicallly used in mixed signal circuits)? I have seen dual gate process so that we can double the supply voltage so that we can have higher output swing...and so on...
I understand that thicker gate process endures (...)
Analog Circuit Design :: 06-19-2006 17:49 :: ee484 :: Replies: 0 :: Views: 576
i mean like(strained silicon) (triple gate mos) finfet) ....etc
Analog IC Design and Layout :: 11-27-2008 16:49 :: THUNDERRr :: Replies: 6 :: Views: 1120
triple means the package includes 3 of these NOR gates. Positive means the gates are responding to positive logic states (high (or "1") is active, low (or "0") is inactive). Valid for inputs and output.
Electronic Elementary Questions :: 09-16-2014 14:42 :: erikl :: Replies: 2 :: Views: 113
Am new to this groups and novice in hardware stuff.
I found that
If (in protected mode) A20 gate is used to access odd megabytes.
and is used to reset the cpu so that we can go back to real mode from protected mode.
In another article i read that triple faulting also used to reset the cpu.
1. if present day OS boots at prote
Microcontrollers :: 09-21-2006 08:51 :: sureshkumarp :: Replies: 0 :: Views: 409
We need to know the range of voltages you are trying to pass.
If it includes the negative range, are you sure that your process has triple well capabilities to support it?
Analog Circuit Design :: 03-07-2011 06:25 :: checkmate :: Replies: 5 :: Views: 2476
basically the substrate isolation. triple well transistors are more isolated.
Analog IC Design and Layout :: 11-12-2008 04:43 :: khouly :: Replies: 9 :: Views: 14802
We are using IBM 65nm cmos10lpe process.
Our design used a triple-well RF nfet (nfettw_rf). However, when we checked DRC with Calibre, the tool generated the following result:
"triple well tie-down rule: must touch RX, which is electrically connected to (RX over NW) through M1"
Could you plea
Analog Circuit Design :: 10-18-2009 23:22 :: chickenvlsi :: Replies: 1 :: Views: 2376
I'd like to ask you a question regarding the triple well MOSFET:
In the schematic view, it is supposed that a triple well mosfet has an extra terminal?
Analog IC Design and Layout :: 04-22-2014 12:31 :: AMSA84 :: Replies: 2 :: Views: 218
does anybody of you know a mixed gate ic, which includes different logic elements like (and, or gates) in the same package ?
hope for info, SyNTaXer
Professional Hardware and Electronics Design :: 04-22-2002 10:49 :: SyNTaXer :: Replies: 1 :: Views: 985
I am looking for a low noise inverter chip (8pins) to generate the negative voltage for biasing GaAs Fet's gate.
I tried the Maxim and Linear Technology chips. They performed good but they did'nt accomplish with the temperature range requiride.
Does somebody suggest me some other manufacturer?
Thanks in advance
Other Design :: 07-10-2002 21:01 :: nandopg :: Replies: 2 :: Views: 2023
Synopsys Power Compiler can use integrated gate-clock cell (Latch type) to implement a low power design. Which StandCell Library support the integrated gate-clock cell (Latch Type) that can be used by power compiler ?
ASIC Design Methodologies and Tools (Digital) :: 07-21-2002 02:07 :: S0933263236 :: Replies: 7 :: Views: 2201
When Verilog/VHDL design(s) are synthesized into the gate-level netlist, how do you import the netlist into ECS schematic environment ?
Because I am doing the digital design, and I use the ECS schematic to do the module interconnection. In order to integrate the whole design into the same database, I hope to translate the gate-level netlist int
ASIC Design Methodologies and Tools (Digital) :: 10-02-2002 23:42 :: joe2moon :: Replies: 5 :: Views: 2560
Since Dual-gate FET is a four-terminal device, the traditional model of S-parameter S2p is not enough to model the device. Anyone who have experienced on it because it is quite common employed in Mixer design ?
RF, Microwave, Antennas and Optics :: 01-04-2003 04:13 :: Rayengine :: Replies: 3 :: Views: 2279
Could someone tell me how to do gate Level Simulation? Thanks
Professional Hardware and Electronics Design :: 01-13-2003 15:14 :: fireman :: Replies: 2 :: Views: 1212
Every time when I do the gate level simulation, I get a lot of troubles such as the simulator is dead, the result is not waht I want, ..., I am wondering if my method has some problem.
Any good book about the flow chart to do gate level simulation (including the EDA tools) for ASIC and FPGA?
Thaks a lot.
RF, Microwave, Antennas and Optics :: 02-11-2003 22:47 :: fireman :: Replies: 4 :: Views: 1740
layout results have Flat Multi-Million gate ASIC Designs Using ASTRO
ASIC Design Methodologies and Tools (Digital) :: 02-14-2003 09:04 :: bravobravo :: Replies: 0 :: Views: 778
I learned how to simplify logic terms with one output variable by Karnaugh Veitch-Diagrams or simple boolean algebra in combinatory logic.
But how do I get the leaste gate count solution for for example two output variable which are using the same or part of the same input variables?
is it somehow possible to state a count of components(for exa
Hobby Circuits and Small Projects Problems :: 02-17-2003 00:44 :: dsp_ :: Replies: 0 :: Views: 1602
Need to shut down a small signal dual gate mosfet amp
the idea is to switch off the amp during transmit in a transciver ?
Professional Hardware and Electronics Design :: 03-08-2003 16:32 :: bobcat1 :: Replies: 1 :: Views: 1032
When I synthesis the same rtl code for different asic libraries in leornad0. I am getting different gate counts. Does anyone knows why is this.
ASIC Design Methodologies and Tools (Digital) :: 03-27-2003 23:29 :: eda_wiz :: Replies: 5 :: Views: 1347
Could you explain simply the FET gate Common Mode
Parameters diagrams given in datasheets?
S11 is the reflection coefficient of the input
S22 is the refleciton coefficient of the output
S21 is the forward transmission gain
S12 is the reverse transmission gain (from output to input)
There are polar graphs but I don't know what does
RF, Microwave, Antennas and Optics :: 04-02-2003 08:01 :: Sobakava :: Replies: 0 :: Views: 1003
Open-Source path to multi-million gate Verilog+VHDL designs
1. -> t
Software Links :: 04-03-2003 08:58 :: jimjim2k :: Replies: 0 :: Views: 545
Signs - free gate-level logic synthesis, analysis and simulation based on a VHDL subset.
1. -> t
Software Links :: 04-03-2003 09:00 :: jimjim2k :: Replies: 0 :: Views: 653
Here is something that came out of a discussion not long time ago - what is faster - source follower or common gate amplifier? Assume the same conditions for both - same bias current, same load capacitance, same size of transistors. Any opinions?
Professional Hardware and Electronics Design :: 06-17-2003 17:35 :: sutapanaki :: Replies: 7 :: Views: 2051
i want to decode a 22v10 PAL, and understand the complete gate logic implemented in it. help from anyone of u will greatly solve my problem
Professional Hardware and Electronics Design :: 09-06-2003 16:51 :: kalpatish :: Replies: 0 :: Views: 1118
Xilinx advertizement or datasheet says about the size of FPGA as System gate.
Does anyone know how to come up with the calculation of the system gate?
The largest Virtex-II XC2V8000 is about 8 M sytem gates.
Does this mean I can implement 8M logic gates? I guess this is definitely not possible.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-12-2003 21:02 :: simon2kk :: Replies: 3 :: Views: 2295
I am looking a CPLD.
I need 512 or more FF stage and 8000 gate array but usualy this type IC has more pins.
Iam looking around of 24 I/O.
Do you know this type CPLD?
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-02-2003 10:52 :: bunalmis :: Replies: 1 :: Views: 1002
I am trying to find a mosfet gate driver design that I can use in PSpice simulation. Are they only available as i.c's or does anyone have a specific design? I am trying to use the mosfet as a switch in a dc-dc boost converter.
Thanks for any help that you can provide.
Professional Hardware and Electronics Design :: 12-08-2003 13:56 :: ee01akk :: Replies: 25 :: Views: 16305
Looking for e-books or papers on triple band LAN
What is the advantage and disadvantages
RF, Microwave, Antennas and Optics :: 12-25-2003 04:38 :: gladiator :: Replies: 4 :: Views: 681
I want to design a class d output. who can give me some gate driver design document. Thansk
Analog IC Design and Layout :: 03-07-2004 22:28 :: gqxfw :: Replies: 2 :: Views: 1715
Does anybody know how to convert spice gate level nelist to verilog netlist? Please help me .
thanks a lot.
ASIC Design Methodologies and Tools (Digital) :: 03-24-2004 09:32 :: taoly :: Replies: 3 :: Views: 2347
How to calculate gate count in synopsys. Is there need to map to any library to check the gate count
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-15-2004 08:08 :: shiva_mag :: Replies: 4 :: Views: 2682
Can anybody show me how to calculate the gate resistance(Rg) in a MOSFET? It's better to give some example on calculation or simulation on that matter!
From 'Impact of Distributed gate Resistance on The Performance of MOS Devices' by B.Razavi, R.Hong Yan and Kwing F.Lee it shows that there is a relation between Rg/3 and 1/gm.
Analog Circuit Design :: 04-29-2004 22:17 :: guamak_menanak :: Replies: 12 :: Views: 22611
:arrow: There seems no any parameter about "gate Noise" defined in BSIM3v3.2, So the simulation of Noise Figure(NF) doesn't include "gate noise", is it right? :?: :?: :?:
RF, Microwave, Antennas and Optics :: 06-13-2004 23:44 :: cqmyg5 :: Replies: 0 :: Views: 571
Noise Figure obtained from ADS, Is't include "gate noise" or not? :?:
the BSIM3 model doesn't include parameter of "gate noise", How can ADS to get out right NF if it doesn't calculate "gate noise"?
RF, Microwave, Antennas and Optics :: 06-15-2004 06:01 :: cqmyg5 :: Replies: 3 :: Views: 1305
I'm using Modelsim 5.7, an I'm tryng to simulate a gate level netlist.
But if i use an implicit wire declaration es. or2 (siga,sigb,out); the simulator don't attach the net to the module output and I find always X.
But i if I check the module itself it behaves correctly.
Do anyone know if exist a directive for modelsim to compile thi sctruct
ASIC Design Methodologies and Tools (Digital) :: 06-16-2004 05:13 :: fant123 :: Replies: 0 :: Views: 1104
hi to all
I need plain program about
Logic gate user flash or Microsoft power point or Microsoft publisher
ASIC Design Methodologies and Tools (Digital) :: 07-08-2004 17:46 :: oawam :: Replies: 1 :: Views: 912
I have read a great deal of articles, and evaluated several varieties of charge pump cell in both CMOS & bipolar - has anyone else studied or built charge pumps? I'd like to open a discussion.
I'm talking mostly about integrated charge pumps, suitable for 100-200uA of high voltage generated inside an IC. The applications are:
-Hot swap and s
Analog IC Design and Layout :: 07-13-2004 21:24 :: electronrancher :: Replies: 2 :: Views: 1172
I'm curious to know what kind of applications need 100M gates in a chip? :?
ASIC Design Methodologies and Tools (Digital) :: 07-14-2004 09:16 :: SC3K01 :: Replies: 6 :: Views: 979
HOW to Clock gate DW IP ?
I connected "CLK & EN" to CLK of DW IP but my boss says this is not acceptable.. anyother ways...
ASIC Design Methodologies and Tools (Digital) :: 07-15-2004 21:36 :: eda_wiz :: Replies: 2 :: Views: 497
is there any tool that can convert the gate level netlist of a particular std cell library to its equivalent layout .... the tool should read in the gate level netlist and also the layout of std cell library and generate the layout of the final netlist...
Software Problems, Hints and Reviews :: 07-19-2004 12:31 :: rogger123 :: Replies: 1 :: Views: 1210
In the old process , some was appied to metal gate in the mos transistor , but with development of Si gate, Metal ( AL) gate process was replaced by SI gate? Who could tell me the disadvantages in the AL gate process? TNANKS!
Analog IC Design and Layout :: 08-04-2004 06:08 :: beckwang :: Replies: 3 :: Views: 1140
Would any one be able to help me in modelling a double gate transistor using VHDL-AMS.
or any material on double gate transistors??
below is the VHDL-AMS code for a single gate transistor....
is there a simple way to modify it ??
ASIC Design Methodologies and Tools (Digital) :: 08-17-2004 07:47 :: rogger123 :: Replies: 0 :: Views: 958
I'm confused about this problem.
ASIC Design Methodologies and Tools (Digital) :: 09-01-2004 09:58 :: craftfox :: Replies: 5 :: Views: 1454
The manual said for gate-level, producing forward-annotation SAIF just follow 2 steps:
1) I am confused. Doesn't it need read in gate-level netlist? If don't need, how does DC know what or which information it should write to saif file, but not all information in library?
2) When I use read_lib, DC told
ASIC Design Methodologies and Tools (Digital) :: 09-16-2004 04:17 :: qjlsy :: Replies: 1 :: Views: 1711
can someone show me the gate level implementation of digital sigma-delta modulator
Analog IC Design and Layout :: 09-20-2004 00:49 :: xusoso :: Replies: 0 :: Views: 626
I forgot what are the important properties of these amplfiers/buffer: CMOS common source, source follower, common gate amplifier
:?: I need to know their:
1. input/output impedance (high or low)
2. what they are normally use for
3. gain & BW
Analog Circuit Design :: 09-21-2004 09:28 :: wylee :: Replies: 2 :: Views: 3010
I am using umc technology library for synthesis
how can I calculate the gate count of my design if I know the cell count.
moved here from DSP by davorin
What the hell it has to do with DSP????
Post in right section next time or you'll risk to get warning
ASIC Design Methodologies and Tools (Digital) :: 09-22-2004 12:10 :: jayant :: Replies: 7 :: Views: 5129
I need a schematic (gate and transistor level) for a I2C interface.
Topic moved, posted in wrong forum.
Professional Hardware and Electronics Design :: 09-24-2004 07:52 :: SwordFish :: Replies: 2 :: Views: 1383
I am using Precision Synthesis to do VHDL design. Some time when I do synthesis, it doesn't give all gate level circuit.
Any one knows how to sysnthesis a digital circuit only with gates?
ASIC Design Methodologies and Tools (Digital) :: 10-07-2004 14:01 :: isaacnewton :: Replies: 9 :: Views: 1434
I am designing a Limiting Amp, process is ST0.13um, when W/L=23/0.13, the BW is about 3GHz, but if gate fringer number >1, the BW is larger with peaking. As I knew using fringer configuration can reduce the Capacitance of gate, becasue of the areas shared, But what induce peaking?
Is there any theory to explain this? Thank you in advance.
Analog IC Design and Layout :: 10-09-2004 08:53 :: rats :: Replies: 1 :: Views: 983