61 Threads found on edaboard.com: Two Stage Cmos Opamp
what is two stage cmos opamp. whwre is it used
Electronic Elementary Questions :: 13.01.2005 14:20 :: aman :: Replies: 8 :: Views: 1612
We are designing a two stage cmos opamp using cadence 180 nm technology.We tried P E Allen Text book procedure but the output is getting saturated.We are not even getting the high gain.Can anybody suggest us the design which will give us around 80db gain.We need it for a comparator in SAR ADC.Please try to give the hand (...)
Analog Circuit Design :: 18.04.2012 02:56 :: gundaljk :: Replies: 0 :: Views: 374
I am designing a two stage differntial opamp. I am not sure if i have to design two CMFB or just use one for both. Im not really sure what the difference is. Does anybody know?
Analog Circuit Design :: 18.11.2007 20:38 :: QT_GIRL :: Replies: 14 :: Views: 997
How to designa two stage cmos chopper-stabilized OP? I want to use in bandgap.
Analog IC Design and Layout :: 12.12.2007 04:15 :: wells001 :: Replies: 2 :: Views: 898
I am new to analog design and want to practise my skills.
can someone give me specs for 2stage cmos opamp design
Analog Circuit Design :: 27.06.2010 21:27 :: crazy4analog :: Replies: 0 :: Views: 470
i m final yr student and doing a 2 stage cmos opamp design. i have completed the design of the individual stages of the opamp like the current mirror, diffamp etc, i want to know how to join/interface these two stages .i.e the op amp uses the amplifiers which r (...)
Analog Circuit Design :: 01.07.2005 14:04 :: shankar :: Replies: 1 :: Views: 600
Can someone please explain the impact of load capacitor on the Slew Rate of a standard two stage op-amp?
In addition, can the use of cascoded miller compensation improve the slewrate performance of an op-amp?
I will appreciate if someone can point out the method to derive the slewrate formula for both cases.
Analog IC Design and Layout :: 05.12.2007 20:15 :: sachinagg77 :: Replies: 5 :: Views: 1336
Can anyone propose good books or papers on the design of cmos operational amplifiers? I am particularly interested in the traditional two stage cmos approach (a differential pair and a common source with active loads). Please post any files or links
Analog Circuit Design :: 08.11.2008 09:44 :: saruman1983 :: Replies: 0 :: Views: 589
First of all,since you have already studied about basic concepts of cmos opamp,then the next step is to choose the circuit topology that will implement your amplifier.I suppose that the opamp you are designing is for academic/training purposes and not straightly intended for production,so starting with the design of the (...)
Analog IC Design and Layout :: 17.10.2010 07:15 :: jimito13 :: Replies: 3 :: Views: 1643
If you dont want to change the architecture then there are two ways of increasing gain
1)Decrease the biasing current
2)Increase the W of the input n channel diff amplifier
Analog IC Design and Layout :: 04.01.2006 23:13 :: Chethan :: Replies: 5 :: Views: 1425
you can use the two stage cascode opa
Analog Circuit Design :: 12.04.2006 03:39 :: dasong :: Replies: 4 :: Views: 3273
how to obtain good PSRR for two stage amplifier?
My stability is ok as i have put compensation cap at the 2nd stage..
thanks in advance..
a paper has explained it.
<cmos op amps with improved psrr and common-mode input range>> by david b.ribner & miles a.copeland
Analog Circuit Design :: 07.09.2006 01:07 :: renwl :: Replies: 5 :: Views: 1699
Hi. Is anybody of you have idea how to increase the loop gain in a two-stage opamp (cmos). My circuit is the simpliest two stage opamp. Now i have 55db and i want to reach 75db at least.
one way is simply increase the gm of the first stage (...)
Analog Circuit Design :: 23.04.2007 22:51 :: dodoro :: Replies: 2 :: Views: 1876
It is up to the load and your application. Cascode OTA is a good choice, but opamp can also be designed. Just use two stage.
Analog Circuit Design :: 27.04.2008 02:00 :: jecyhale :: Replies: 7 :: Views: 1388
Don’t use a two stage approach; you will burn too much current in the second stage.
Unity Gain Bandwidth = 500 MHz => for stability second pole should be around 1.5 GHz!!!!!
Second Pole = gm(second stage)/(2*pi*Cload), believe me that will cost current.
Normally a folded cascade should be enough to reach 75 dB, (...)
Analog Circuit Design :: 16.06.2009 10:58 :: edge_tv :: Replies: 2 :: Views: 1689
i want to design a two stage opamp with cascode compensation, just as the picture below shows. i use the capcitor Cc for compensation between node A and C, my question is, how to choose the value of Cc?
You can read Page305 of "design of analog cmos integrated circuits" written by Razavi.
this is a more effective co
Analog Circuit Design :: 22.09.2009 02:31 :: mengcy :: Replies: 7 :: Views: 2141
It is a quite common cmos amplifier you mentioned. You can find a design procedure in Ken Martin's 'Analog Integrated Circuit Design' book. A two stage amplifier should fulfil your purpose.
Analog IC Design and Layout :: 04.03.2005 01:58 :: willyboy19 :: Replies: 11 :: Views: 1864
yes, I agree aryajur's suggest.
For 1 stage, if high gain is needed, we can use gain-boost tech.
For 1 stage, there is also two structure: cascode and folded cascode.
Analog IC Design and Layout :: 30.06.2005 22:34 :: sunking :: Replies: 13 :: Views: 1902
i am doubtful whether simple two stage class-A opamp can provide 160MHz UGB.please clear me if i am wrong.i thing we have to choose the folded cascode opamp for 160MHz ugb.
Analog Circuit Design :: 31.08.2005 00:55 :: avinash :: Replies: 8 :: Views: 1404
can some one help me how to design this project?
STEP BY STEP PLEASE!!!
from what i should start and with wich to continiue
i can not obtain all these features att all.
i should use hspice
1. Obtain the features below at lowest power consumption possible at FF and SS corners of 0.35um cmos.
2. Design bias circuits
Analog Circuit Design :: 17.12.2005 14:13 :: ehs dav :: Replies: 5 :: Views: 1363
you can use folded cascode with pmos i/p pair. as it has the moderate gain and speed more than two stage.
my plan is to use an pmos folded cascode with a source follower,the 1st pole(pole of first stage) is dominant pole,and source follower has the 2nd pole.from the settling time requi
Analog Circuit Design :: 06.01.2006 02:01 :: dayang :: Replies: 7 :: Views: 1188
2.two stage with miller compensarion
3.not start wit spice but calculate
Analog Circuit Design :: 20.07.2010 20:49 :: tuza2000 :: Replies: 7 :: Views: 2499
In the first the capacitor makes the level shifting and the use of NMOS is better due to the higher gm for the same current than in the second case. That means the first case will be better in terms of stability with less current since this is a two stage topology.
Analog Circuit Design :: 16.02.2007 14:30 :: bastos4321 :: Replies: 3 :: Views: 742
transistor is single stage amplifier where as opamp is two stage amplifier.
it can be 3 or more depend on the spec
Electronic Elementary Questions :: 04.06.2007 13:15 :: tomdchao :: Replies: 7 :: Views: 5127
I am designing a two stage differntial opamp and i need to get a swing of 0.8 V using 1.8V supply. I have to compenstate the opamp. I am not quite sure what is cascode miller compensation using a CG amplifier. Can somebody please clearify that?
I have to also use CMFB. Im not sure if i can use one CMFB for the (...)
Analog Circuit Design :: 17.11.2007 22:53 :: QT_GIRL :: Replies: 4 :: Views: 1126
Any notes or reference for designing single supply based two stage miller all cmos books the design examples are based on dual supplies.how do i go about designing it for single supplies.
Analog Circuit Design :: 27.01.2008 10:04 :: hacksgen :: Replies: 5 :: Views: 1180
I was wondering why analog design books dont
present common mode feedback circuits for single ended two-stages op-amp.
Can someone propose a CMFB circuit for design of single ended differential cmos op-amp?
Analog Circuit Design :: 13.04.2008 08:48 :: yanivh :: Replies: 6 :: Views: 1330
I think the length of the second stage depends on what you want. If you use the first stage as an error amplifier to drive a pmos like you design a LDO, it is better to use smaller size. For conventional two stage amplifer design, I think it is better to keep the length of M16,M6,M7 the same to reduce offset, (...)
Analog IC Design and Layout :: 11.09.2008 22:38 :: yschuang :: Replies: 5 :: Views: 3535
The file attached is one of the best sources of information for two stage op-amps.
I used it in a student project of mine. It worked vary well.
Analog IC Design and Layout :: 13.10.2010 04:11 :: eladla :: Replies: 2 :: Views: 1433
Iam designing a 2nd order 16 bit Delta-Sigma ADC, i need to design two opamp's for two integrators. What difference should be there for both the opamp's in two integrators.Plz reply, i will be happy to reply on any clarification about the question.
Electronic Elementary Questions :: 26.12.2010 01:55 :: srudeep :: Replies: 3 :: Views: 792
I am trying to design an op-amp with rail to rail inputs and am finding an issue with the symmetric input stage trick. I am limited to a process with no floating gate and nothing fancy like triple well.
I have tried two approaches, one with a simple dual (symmetric) nmos and pmos differential pair and also with a dual folded cascode approach (se
Analog Circuit Design :: 28.04.2011 12:38 :: phoenixosu :: Replies: 0 :: Views: 620
Here are the specs for the opamp I have:
180 nm cmos
DC gain: 40 dB
Gain at 20 kHz: about 30 dB
Total current should be less than 10 nA
With a two stage, miller compensated is this possible (assuming subthreshold bias at the NMOS inputs)? Any other ideas?
Analog Circuit Design :: 29.09.2011 07:51 :: analogLow :: Replies: 3 :: Views: 624
I have problem with opamp transient simulation. I´ve designed several one stage structures (folded, telescopic, symetrical cmos) and all made same problem. In attachment file is simulation connection - R ratio is 1. So If I have input sinus amplitude 1 V, output amplitude is not 1 V but a little bit smaller. I don´t know, where is (...)
Analog Circuit Design :: 06.12.2011 11:08 :: vilemk :: Replies: 2 :: Views: 517
If convenient, can you post what you have here? It's not readily understood what's meant by conventional two-stage amplifier?
I thought it's better so that it's easier for those who can help you.
Analog Circuit Design :: 10.02.2005 20:44 :: lastdance :: Replies: 5 :: Views: 1903
can some one help me how to design this project? STEP BY STEP PLEASE
i should use hspice
1. Obtain the features below at lowest power consumption possible at FF and SS corners of 0.35um cmos.
2. Design bias circuits
3. Design proper switching CMFB for two high impedance nodes of OTA
Target features of design are:
Analog IC Design and Layout :: 15.12.2005 20:29 :: ehs dav :: Replies: 0 :: Views: 826
Normally gate and drain are high impedance node, while source is typically low impedance. But it is not always true. If the transistor is diode connected, the impedance of drain and gate will be reduced.
For a two or three stage opamp, the highest impedance node is normally the output of gain stage. You could find that (...)
Analog Circuit Design :: 04.04.2006 22:58 :: cookey :: Replies: 4 :: Views: 2530
You can use a two-stage hysteresis comparator like that shown on page 475 of the Allen and Holberg cmos book (2ed).
Analog Circuit Design :: 03.05.2006 17:24 :: johnsmith101 :: Replies: 4 :: Views: 1038
I think you should give more details of your circuits . The LDO'S PSRR may be dominated by the error amplifier. In general, the two- stage opamp has poor PSRR at high frequence,because of the miller compensation capacitor. So you can try the telescope & folded cascode structure.
Analog IC Design and Layout :: 08.06.2006 08:23 :: jeff_zx :: Replies: 6 :: Views: 1845
i've got a problem with comparator. it should take as little current as possible.
firstly i've designed two-stage comparator with 10uA bias current for each stage.
Output's voltage drives a big transistor key(W=5m L=0.5u),which discharges capacitor. Output's falling time is long, so the key isn't turned off when it should have. (...)
Analog IC Design and Layout :: 19.06.2006 17:45 :: jutek :: Replies: 2 :: Views: 678
Please refer to the paper "A 3-V 340-mW 14-b 75-Msample/s cmos ADC with 85-dB SFDR at nyquist input, jssc,vol. 36 no. 12 Dec. 2001". A two-stage amplifer has been presented with 100-dB of open loop gain and 2-GHZ GBW by using the 0.35-um cmos process.
Analog Circuit Design :: 31.07.2006 11:05 :: ericliu :: Replies: 29 :: Views: 3038
it's a very challenging task.
1.2v is very low and the sampling rate is too high. so i will prefer to two stage.
Analog IC Design and Layout :: 22.11.2006 21:24 :: renwl :: Replies: 5 :: Views: 1292
I'm trying to implement a 10-bit 20MS/s pipeline ADC in 0.25um cmos technology. In designing 1.5bits/stage, I have two questions:
1. In switched-capacitor sample-and-hold circuit, I use cmos transmission gate to implement switch. Usually NMOS and PMOS have same size or different size? For C=1pF, which size is better, (...)
Analog Circuit Design :: 06.12.2006 20:17 :: pfd001 :: Replies: 2 :: Views: 961
Can anyone please provide materials regarding the calculation of the transfer function of two stage and telescopic op amps...........
Thank you in advance.
Analog Circuit Design :: 11.04.2007 22:10 :: barath_87 :: Replies: 6 :: Views: 1877
if you want to reduce 1/f noise, two techniques can been thought of--chopper and auto-zeroing.
Analog Circuit Design :: 15.04.2007 23:19 :: xusoso :: Replies: 6 :: Views: 1366
follow the following book , this is having two stage comparator design, which is useful for beginers.
vlsi design techniques for analog and digital circuits by geiger
Analog Circuit Design :: 25.05.2007 05:46 :: ravitest :: Replies: 6 :: Views: 1036
for the mentioned specs even conventional two stage opamp is suitable.
Which technology u r using?.
Well the design procedure is not fixed is changes according to what u want.
Analog Circuit Design :: 06.05.2008 04:01 :: amitjagtap :: Replies: 13 :: Views: 1170
Can any one say why a diffrential amplifier is preffered inside an Operational Amplifier?Does it have any special advantage?
Yes, it has. It has two inputs - one inverting and one non-inverting (if compared with the output phase). And that is important for a device which can be used as a universal amplifier in several fu
Analog IC Design and Layout :: 22.12.2008 04:34 :: LvW :: Replies: 4 :: Views: 2219
Is it possible to design the filter with cutoff frequency = 100 MHz and the SFDR > 70 DB with 70 MHz Input? The process is 0.35um cmos.
Is it possible to implement it in active RC?
In active RC, the opamp should have enough loop-gain at 100MHz to ensure the linearuity, right? If I use two stage opamp (...)
Analog Circuit Design :: 29.07.2009 05:25 :: frozenduck :: Replies: 1 :: Views: 907
There are many, many rail-rail I/O op amps out there
as commercial piece-parts. If you need both ends to be
at- (or over-) rail, you may end up with two follower-
buffered diff pairs (one N, one P) so that when one is
cut off the other is still working. Then the trick is in how
to cleanly combine the two, across the CM range.
Check out all
Analog Circuit Design :: 16.09.2009 14:39 :: dick_freebird :: Replies: 4 :: Views: 1200
Is is correct to use two different channel lengths in 2 stage opamp design ??? Sure, why not?
I am using 0.18? cmos tech.
I am using L = 0.54? in stage 1 and L = 0.18? in second stage.
Will it cause offset ?
Not if used in different stages. Yes, if done with (...)
Analog IC Design and Layout :: 06.06.2010 07:35 :: erikl :: Replies: 2 :: Views: 543