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Hi. When I running simulations rocketio in ModelSim show this error: Error: (vsim-3043) fibre_mgt.v(154): unresolved reference to 'ALIGN_COMMA_MSB' in GT_FIBRE_CHAN_INST.ALIGN_COMMA_MSB. # Region: /top_mgt/mgt Why??? Thanks
Hi all.. When i run dft_drc scan.spf i get a error like this. scan.spf is my spf file.. unresolved reference (Signal "x"is not a netlist pin). (V5-1) What will be the reason for this? Kindly help me.
Hi I am using Modelsim_xe ver6. When I try to compile some design I get this error "Error: (vsim-3043) C:/Xilinx/verilog/src/uni9000/FDCE.v(31): unresolved reference to 'glbl' in glbl.PRLD." How to overcome this error? another note: Xilinx library is not @ that location "C:/Xilinx/...", and even after copying the Xilinx library to that
Hi I used Flipflop primitive from language templates of Xilinx ISE9.1i in my design. Problem- When i try to simulate the design using modelsim. iam getting error like this.. project open {C:/Documents and Settings/keshago/Desktop/tetbench/flop} # Loading project flop # Compile of tesflop.v was successful. vsim -L {C:/Documents and Se
Hi everyone, I am getting some errors while running Tmax during DRC: How to overcome these errors.. DRC> set drc /home/student1/sk4xilinx/proj4/proj4stil.spf run drc ------------------------------------------------------------------------------ Begin scan design rules checking... ----------------
I would like to see the inside of a module, without using a port module submodule (a,b,c); . . reg subtest; . . . endmodule module _main (testout); submodule _sm(a,b,c); assign testout=_main._sm.subtest; endmodule synplify report error: unresolved hierarchical reference _main._sm.subtest I do
You can find it in dir where you have installed modelsim. Here is one for ur reference std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib ; Turn on V
hi i m using Uvision3 Keil compiler. i wat to create my own library(of functions).how to make that and how to use tha lib in my main files. i tried this with option create lib in the compiler . it it creating lib files but i use this there is error like *** WARNING L23: unresolved EXTERNAL SYMBOLS *** ERROR L128: reference MADE TO UNRE
Dear all : when i simulate my codes with NC-Verilog after synthesizing them with DC,some reference errors appear,the errors is list as follow: ncelab: *E,CUVMUR: instance of module/UDP 'fdesf1a3' is unresolved in ''. ncelab: *E,CUVMUR: instance of module/UDP 'clk1a3' is (...)
hi....i interface my assembler code into code is #include void sakthi(); void main() { sakthi(); } void sakthi( ) { #pragma ASM MOV A,R0 MOV R0,A #pragma ENDASM } ..but i get some warning messages like WARNING L1: unresolved EXTERNAL SYMBOL SYMBOL: ?C_START MODULE: STARTUP.obj (?C_STARTU
I was planning to run Formality to verify my SV design. In Stage 1 (reference) I feed the file, and it accepts without an error. Now when I try to set the top module, I run into several warnings and at the end Formality stops and fails to set the top module. I get warnings like these: ... ... Warning: Cannot link cell '/WORK/example/U112' to
Hi Daffo123, This reminds me a problem I encountered with gds export from Magma. The problem may be unresolved cells or conflicting reference cells during gds export. Normally gds is merged using gds files of reference cells inside a design, e.g. macro gds files, standard cell gds files, analog cell gds files. Please check the log file (...)
hi everybody Can anybody tell me how to resolve the following error?? I created dll and trying to use the dll in another project. unresolved external symbol "public: static int __cdecl Dll::add(int,int)" (?add@Dll@@SAHHH@Z) referenced in function _main I copied and pasted the .lib and.h and .dll file in the new project folder and using
Hi~ I want to do a fast simulation by removing a complex module (CALC). Then I used generate statement like this below: generate if (fast_sim = = 1) begin CALC u_calc( ); end endgenerate However, I find that I can't refer the u_calc module in SIM_TOP which needs to defparam a parameter in u_calc module. I have tried u_fpga_top.u_calc