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21 Threads found on edaboard.com: **Unsigned Multiplication**

The SIGNED/**unsigned** setting of lpm_add_sub actually matters, but only for the optional overflow output.

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-25-2016 10:30 :: FvM :: Replies: **9** :: Views: **1060**

Hi,
There are many ways to do it:
An easy to understand method:
* To find out sign of result: XOR both input sign bits
* then make both inputs positive ( ==> only 3 bits **unsigned**)
* multiply both values: 3 bits x 3 bits = 6 bits result
* If the result is negative (output of XOR) then invert the **multiplication** result
* form a 7 bit sign

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-19-2016 10:56 :: KlausST :: Replies: **1** :: Views: **805**

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-10-2016 08:09 :: FvM :: Replies: **13** :: Views: **782**

Hello,
i have to design 32 bit alu unit that do normal **unsigned** **multiplication**, booths **multiplication** and **unsigned** division
In binary format, i know that we multiply lsb by of the one number by the other number
and then we save the result in some register , and then we get the bit next to the lsb we multiply and (...)

ASIC Design Methodologies and Tools (Digital) :: 04-02-2016 14:45 :: abukharmeh :: Replies: **3** :: Views: **833**

x must have an **unsigned** int16 type, otherwise you'll get an overflow in the **multiplication**.
164 means?
x=input data(0 to 255)? correct or not?
The input value x is assumed with a range of 0 to 398, as asked in your post. I suggest to check the method yourself by putting in different values.

Microcontrollers :: 05-29-2013 16:48 :: FvM :: Replies: **3** :: Views: **574**

I assume you are talking about **unsigned** **multiplication**. If you are, then you'll never get overflow under the stated conditions.

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-11-2012 18:20 :: barry :: Replies: **1** :: Views: **519**

Nice explanation:: When you make an assignment or port connection form a signed data type to an **unsigned** data type, the signedness of original data is lost. Only the individual pattern of bits is transferred.

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-14-2012 13:49 :: yourcheers :: Replies: **4** :: Views: **1623**

The following routine is a 10-bit X 10-bit assembly routine written by Martin Sturm for the PIC18F series:
; Multiply 10bit by 10bit **unsigned**
; by Martin Sturm 2010
; Tested over full range of 10bit input combinations
;
; a (10bit) = aH:aL (not modified)
; b (10bit) = bH:bL (not modified)
; aH:aL * bH:bL --> rH:

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-08-2012 00:43 :: bigdogguru :: Replies: **8** :: Views: **2375**

To multiply two's complement, the sign bit must be treated differently.
For any **multiplication** of two n-bit numbers, the least significant n-bits for two's complement and **unsigned** numbers are the same. If you use a 2n-bit result, the most significant n-bits will be different.
You will get the correct results if you increase the number of bits

Elementary Electronic Questions :: 07-07-2012 18:58 :: tkbits :: Replies: **3** :: Views: **1288**

The error will be fixed like this:
variable prod :t3:=(others => (others => 0 ));
In your code you're trying to assign a numerical array type (like an **unsigned** or signed), but an integer is not an array of bits or std_logic.
A few notes on the code:
1. variable i,j,k : integer:=0; - Not required, they are declared in the loops
2. I hope this is

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-17-2012 10:47 :: TrickyDicky :: Replies: **27** :: Views: **3649**

Hi there,
Recently I was trying to write a Verilog Code for **multiplication** by 3.
Condition-My Input is variable-**unsigned** or Signed
My Multiplier is fixed-3
So if i have -20 as input in binary my output should by -60.
and 20 as input my output should be +60.
I want to declare only one output that is product and depending o

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-05-2010 19:11 :: er.twi.fb :: Replies: **4** :: Views: **3978**

VHDL has **multiplication** and divide functions for signed/**unsigned** numbers. Its as simple as writing the following code:
op <= a * b;
op <= a / b;

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-13-2010 08:39 :: TrickyDicky :: Replies: **6** :: Views: **3516**

Depending on the referenced libraries, the "*" operator is only recognized for specific data types, e.g. signed, **unsigned** or integer.
The support for "/" operator is generally limited and vendor dependant.

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-02-2010 08:53 :: FvM :: Replies: **10** :: Views: **6635**

2) this is regarding AVR ATMEGA8
While doing **multiplication**,division,modulas operation what are the datatypes and format specifiers i should assign to the my resultant strings.
i have used longint,**unsigned** long int,but couldn't success in the manipulation.
If you can show us what you are doing, what is ex

PC Programming and Interfacing :: 06-04-2008 11:05 :: dipal_z :: Replies: **6** :: Views: **1023**

hi,
i am doing a project where i need to do 12 bit signed **multiplication** in VHDL, in ALtera platform. i have done it in two ways -
1) i have done first with **unsigned** library from IEEE, if the nos. are -ve do 2's complement, multiply tw **unsigned** no., then if the sign bit of multiplier and multiplicand are opposite, then do 2's complemen

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-26-2007 04:25 :: amitontop :: Replies: **1** :: Views: **2013**

hi friends am doing alu as my project . . so can any one send the verilog code for tat... its a **multiplication** of 8bit **unsigned** numbers...... pls

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-20-2006 10:27 :: rajakash :: Replies: **3** :: Views: **2528**

I have 3 8-bit std_logic_vectors A, B, C. If I include the **unsigned**.all library, would the code correctly perform the following?:
C <= A + B;
C <= A - B;
C <= A and B; -- bitwise addition
Also for **multiplication**, lets say I have a 16-bit vector called D. Would the following do what I want?:
D <= A * B;
C <= D(7 downto 0); -

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-26-2006 02:35 :: Opel_Corsa :: Replies: **2** :: Views: **869**

Sounds like your compiler is not ANSI C compliant. It should automatically promote your two **unsigned** char values to int before it multiplies them.
The CodeVisionAVR 1.24.7 user manual describes a compiler setting "promote char to int" for ANSI compatibility. Try it.

Software Problems, Hints and Reviews :: 12-14-2005 01:00 :: echo47 :: Replies: **2** :: Views: **2445**

Hi
Try this one.
If we suppose that x0, x1, y0, & y1 are 32 bit then the 128-bit result is:
z = x0.y0 + x1.y0<<32 + y1.x0<<32 + x1.y1<<64
only x1.y1 is signed all other are **unsigned**.
Regards

Digital Signal Processing :: 03-08-2005 18:53 :: Circuit_seller :: Replies: **5** :: Views: **1797**

Has some very nice code snippits. In your case I'd examine this library a bit closer:
It has 8, 16 and 32 bit subtraction, **multiplication**, and division (signed and **unsigned**). Has good comments, should be worthwile...
Happy coding!

Microcontrollers :: 01-31-2005 21:00 :: Gorilla :: Replies: **8** :: Views: **6919**

Take a look here!
**multiplication** is very simple to describe but it requires a large quantity of logic specially for a 32 bit magnitude
a <= b * c;
a b c signed or **unsigned** type or if you want std_logic_vector
bye Stark.

ASIC Design Methodologies and Tools (Digital) :: 01-03-2003 10:20 :: Stark :: Replies: **6** :: Views: **6049**

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