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43 Threads found on edaboard.com: Useful Skew
For me, usefull skew is the skew between flops which have timing path in common. I means, the (normal) skew, is for all flops independently if these flops have no common paths.
You can't. There is no such thing as "no" (zero) jitter or skew. If you had a meaningful, quantitative upper limit to these then you could have a chance of meeting that goal. But if your goal is zero, you may as well quit and go into management before you smarten up and become useful. Then you can have all the =0 goals you want and it's Somebody
many ways to fix setup violation after synthesis. 1. size cell and minimize data path delay. 2. check hold margin and useful skew. 3. use LVT cell if all ways can not work. you 'd better add more margin to re-synthesis or re-design.
also check local and useful skew concepts, know how and where you are going to apply these to time your paths better.
jaya sree, latency numbers can be accepted. Can you tell me if clock skew numbers are global skew or local skew? By any chance did you turned on use of useful skew to meet timing? if that is the case and your timing is good. no need to worry. Jay
Hello every one, For one certain design, data path almost has no margin, so i have to fix setup violation by useful skew. So i check slack margin before/after violation path and set_clock_tree_exception on clock pin. While the result is, some violation was fixed by early/delay clock pin, but some new violat
Hi ajesh, The discussion in the following thread will answer your query.. if you still have any doubts please post here... useful?? cheers
Hi tachyons, Please refer & for setup and hold fixing Hope you find it useful... PS: lot of questions in one day..hmm
Hi Kumar, In all probability there will be setup and hold violations along various paths..depending on whether there are positive or negative skews at the end points... But the thing is we may use the same skew for fixing these violations..this is referred to as useful skew...intentional placing skew to (...)
i've that book... i want to know about useful skew,local skew ,global skew and all those things..it's not given in this book Dear Biku, useful skew:- This is the min skew required to meet both setup and hold violations of a path. Sometimes, what happens, when we (...)
What is useful skew with respect to CTS?.
Significance of Global skew is one need not perform CTO as Setup and Hold Check is already done as useful skew optmizises in such a way that there is no setup violations. For more info:
We usually build a zero skew clock tree first when clock insertion. But If there are some timing violations, we will try to build a useful skew clock tree. The useful skew is the manual skew we add on the clock tree to balance the current timing path and the next timing path.
First a correction: sd and ss are not skews, they are the insertion delays to those registers. Their difference is the skew. Yes, skew can be beneficial in some cases. It is called "useful skew". The idea is that one register-to-register stage can have plenty of positive slack while the next stage has a (...)
Hi all, 1. How operating voltage can be used to satisfy timing? 2. What is the difference between local-skew, global-skew and useful-skew? 3. What is meant by virtual clock definition and why do i need it? 4. Is it possible to reduce clock skew to zero 5. what are problems associated with (...)
Hi all, Please clarify me, What is capacitive loading? How does it affect slew rate? What is useful-skew mean? Din
what is useful skew.how will come useful skew?
What is the difference between skew and useful skew?
hi, i came across this material in magma-da.com. lots of theoritical concepts but i think it wil useful for experienced users. rgds
we can opt timing use useful skew after CTS,and at that time,the clock tree fixed,and the useful skew is based on the fixed clock tree I right? If I'm right,I am wanding when doing CTS,can I tell the SOC-encounter that I will use the skew latter,then the software will not fix some skew that (...)
Hi all, what is useful skew? what will do in Encounter...... Thanks
Another disadvantage - Cannot take advantage of 'useful skew'. useful skew - Clock skew between adjacent filpflops effectively increases the clock period for the same clock frequency, so path delay negative slack is reduced. (slack = effecrive clock period - path delay - setup time).
possible solutions: 1) may be skew constraint is too much tight.....try to reduce it ! 2) u can try with usefull skew optimization
Hi All, I need documents related to useful skew..........
there are places in digital circuits which need delay adjustment like clock skew, and situations which need avoiding hazard and these chips would be useful there........
Hi As far as I know, there will be no pre CTS useful skew.. AS the clock is considered as ideal in pre CTS stage. Post CTS useful skew helps in meeting the timing for critical paths.. If you have a critical path violating timing by 1ns in a 10ns clock and the next flop is meeting the timing by 8ns itself (when (...)
omg so many questions in one post:D........kidding useful skew: when u insert delay in clk path to meet setup slack ... adv: very critical setup can be met disadv: hold might worsen( so should take care of hold) only when one cant meet timing then only one go for useful playing with clk path not recommended.... anyone can co
Hi, Clock latency to every flip-flop is different. The different in the clock latency between two flip-flop is the clock skew. The clock skew can affect the timing budget between the flip-flops. useful skew is the technique to skew the clock so that you have more timing budget on the critical paths.
can any body have useful clock skew material or information . plz upload the material as soon as possible.
Hii hope this is useful, subbu.
Hi Friend.................. this topic is discussed in this sub-forum itself.......... there is also some useful material(PDF)in the topic discussed........... the topic is at 07 SEP 2006 (PAGE 26)............... good luck..................... (if the topic helped you don't forget to push helped me button)
It'said that the design using useful skew for timing optimization is susceptive of the operating condition variation-temperature,voltage,process... And why? zero skew clock tree also have clock buffers which have PVT variance.
hi all, what the major difference between zero skew and useful skew ? in what case we will use useful skew and zero skew and what about timing issues needed to considered and how we can increase clock frequncy with this useful skew i will (...)
refer this pdf it give u some input about usefull skew
Can anybody explain useful skew?How its useful in design with respect to setup and hold?
What is the "useful skew" in SoC Encounter and how to use it? Is it part of an ECO process? Thanks
Hi, It has become necessary to perform hold analysis in worst case corner. I can think of 3 reasons: 1. useful skew. If there is a large skew in the clock tree (e.g. to meet setup time), it is possible that this can cause a hold violation in worst corner, but not best corner 2. Negative setup and negative hold in worst case cell (...)
shankarmit gives a description from on side. And I think it maybe another CTS types: global skew synthesis, local skew synthesis and useful skew synthesis. Global skew : consider the skew between all registers Local skew: only consider the skew (...)
why some skew is usefule?please give me an example,tks!
Pinkesh, search the forum friend.
As the skew increases(positive skew)the setup requirements are reduced. ie.. a circuit synthesised for 150 Mhz may run at 170 Mhz, considering the Clock skew associated with the registers. inshort useful skew refers to the skew which relaxes the timing constraints on the design.
Hi, What exactly is the concept of useful skew in flop based designs and time borrowing concept in latch based designs. Vicky
hi, using magma tools or cadence clockwise to generate clock tree. they can use useful skew to improve the performance.