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14 Threads found on Veilog
Hi all! I'm developing the SD/eMMC controller veilog model and going to simulate it. Now I'm looking for any SD verilog simulation model or eMMC model. I looked though the topics, but didn't find what I need. I checked the denali and samsung pages, but there are no models to download. Can anyone help me to find it ?
sir,for what purpose we combine xilinx(vhdl/veilog) with matlab for particular image processing project. this is for speed or accuracy ?
this code was implemented well on modelsim but how to do it on xilinx ise .... i maen the decimal point numbers handling .... xa=ang+1.570796325; asign = 1.0; xa1 = xa; if (xa1<0) begin xa1 = -xa1; a
Dear all, I am faced with another problem while compiling my simplest hello wordl SysytemC program. Earlier I tried to compile the programs that I downloaded with the systemC official package download and that worked correctly. But now it post errors that are either related to some dll files. I tried the simplest of programs 'Hello world p
hi guys any body please give me the verilog code for 32 bit carry skip adder and 32 bit carry select adder ......its urgent
please somebody tell me how to represent float values in veilog for examle float dummy =0.5......plz
I wrote a behavior model of VCO using verilog-a, then created the simbol. Then, I create a simulation schematic to simulate the VCO in Cadence composer. When I simulation with spectre, I don't know how to set the model libraries, so I just passed it. When I simulated, the simulator said that "Could not open ahdlcmi module library." I don't kno
Hi, I m having 2+yrs of exp in front end digital design, i know vhdl and veilog very well, and currently working in a small concern, i m looking for the change and development in my carrier , any one know any openings in vlsi domain , tell me, my mail id is
it is for time control, when you want to delay a signal by 1 time unit, then the time unit must be defined, this is timescale. best regards Hi could any one tell me what is time scale in veilog... what it defines and why it is used for... Thanks i
in verilog i think you can not use multi dim. array dont forget veilog is HDL no cpu high level language such as pascal or c ....
Hello all, Is there any Nc-veilog tutorials in the forum, if yes please give me the link about the pdf document, else can u provide me the link or some sought of help on how to run the tool, i would be much helpful Thanks Raghu
I know the language "ABEL" can be used on GAL,is there any others can suit this chip,what about "vhdl" "veilog" ?
You cad add symbol of cell that should have behavioral or functional view. Usually it is just veilog code in text format. But anyway you cannot simulate it without LDV package. IC package doesn't include Verilog simulator
The first tool is ldv, it's a toolset from c@dence, the toolset include all ditital simulator from cadence, such as nc-sim, nc-veilog, nc-vhdl, verilog- xl, nc-systemc. The second tools is the Custom IC toolset from cadence, it's include the tools needed for Custom IC, such as vertosor schematic/layout editor, analog artist simula