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28 Threads found on edaboard.com: Verification Completed
I was involved in ASIC design for four years. In our company, I completed two chips. I took part in system design, write RTL codes, FPGA verification, chip synthesis, pt and so on(The work of post layout is done by foundary). But these days,I am at a loss. I dont know which direction is better in the future. So are there any senior engineer
I'm trying to erase a PIC16f877 using Picstart plus and mplab 7.20. Selecting Porgrammer -> Erase device does nothing! On selecting read, mplab seems to be reading the memory ( as seen in taskbar on left bottom) but then I get the message : Device is data protected! Data memory may be invalid. Device is code protected! Program memory may
yes,you can't say verification is completed for design and you can say only that i have done verification of some percentage(%)... the percentages based on your verification strategies. like if you done branch coverage you can say how many branches have you exercised successfully, if you done toggle coverage you can say how (...)
hi all, I completed coding FFT using verilog. I am verifying my output with matlab inbuilt fft operator. As my N (no' of samples are parametrized) for small values of N there no much difference but for N = 512,1024.. some values having difference of +/- 9. I plotted frequency waveforms for my FPGA output and matlab outupt the wave forms are givin
A PCB routing has completed 100% in Blazeroutor, then I pour the plane of the PCB in PowerPCB's Pour manager, In Verify Design,chech connectibity got a "NO ERROR" result, then execute File->CAM, error occors: Clearence checking has been done for the entire design **NO ERRORS FOUND** Latium design rules exist, Run Latium design veri
You should have a digital simulator (eg Logic Design and verification version 5 from cadence?) if you want to run vhdl or verilog. The Cadence IC 5xx do not have digital simulator!
With a master degree in VLSI design, I can not find a job in a year after I graduated. I do not have any employment experience. During the graduate study, I completed three project design including ASIC and FPGA design from HDL coding to physical verification in DSP, and one is the thesis project. I had six interviews about ASIC/FPGA designer or Ph
hi, My name is Raj from hyderabad ,India.I just completed Post Graduate Diploma on IC layout engineering of University of California with sound knowledge on Layout ,Place and Route,verification,CrossTalk.I finished M.Sc(electronics) in march 2006.
Hai all, My name is Raj from hyderabad ,India.I just completed Post Graduate Diploma on IC layout engineering of University of California with sound knowledge on Standard Cell Layout ,Place and Route,verification,CrossTalk.I have good knowledge on STA and logic synthesis.I did project o
The chip design process begins with the architecture design. Once the architecture and operating frequencies are determined, the next step involved is to write the RTL for that. The verification stage takes care of the potential bugs while the RTL is written. DFT is another part thats incorporated in the RTL, so that the design can be tested post f
I do use the calibre for the layout verification. But it becomes difficult to rectify the DRC errors looking at the DRC.db (error database having x-y co-ordintes). Does anyone have any sort of interactive (GUI) for DRC debugging for the calibre in Skill/perl? Thanks in advance Sooraj S Ram
Dear Experts , Iam into a designing of core IP and sucessfully completed it using verilog and functional verification is done using Modelsim se 6.0. My IP core has 5 main modules of which I synthesized 1 module using xilinx ISE 8.1i demo version and the gatecount was something around 122k[/col
Dear Experts , Iam into a designing of core IP and sucessfully completed it using verilog and functional verification is done using Modelsim se 6.0. My IP core has 5 main modules of which I synthesized 1 module using xilinx ISE 8.1i demo version and the gatecount was something around 122k Now i want to synthesize
i am doing downloading to cpld xc95108-20tq100. i get the file .jed which to be downloaded to cpld. i implementded the jtag cable as per the xilinx ........schematics.. then i Erase the program complete successfully, then program get downloaded Programming completed successfully. but then i verify the code it get failed shows an error Ver
What does it mean? The acquisition will significantly expand Synopsys' technology portfolio, channel reach and total addressable market when completed. In acquiring Synplicity, Synopsys will enter the FPGA market segment, where Synplicity is the t
The follwing Error always appear when programming. The sw I use is ise10.1, Anyone can tell me how to fix it? Thanks. Maximum TCK operating frequency for this device chain: 0. Validating chain... Boundary-scan chain validated successfully. '2': Erasing device... PROGRESS_START - Starting Operation. '2': Erasure completed successfully.
Dear sir/madam, I am vinoth , completed BE- ECE in the year of 2007. I am having 3+ years of experience in the field of FPGA/ASIC -RTL Design and verification. Strong knowledge in VHDL and digital electronics. I have been having 3.6 yrs of experience in FPGA (RTL design) field. I am looking for FPGA (RTL) design job. Is there any opening let m
Hi Parvat, May be I can help you with verification. Let me know about your project. My site is Bests,
You will most likely be involved in verification, hence the perl and tcl :cry:
It should be like this. The Micro architecture includes the individual Modules design description, Statemachines involved and Inputs and outputs description of a System. In the case of digital design cycle architecture, it involves not only the design process but verification and validation proceses that need to be followed, tools that are involved
I am working on a DTMF tutorial on Cadence SOC Encounter 9.1. Since this is my first time i am unable to even decide what to do to remove my errors. Presently i have completed CTS and verified the design by connections and geometry. I got almost all of the error after the verification step. I am getting 20 connectivity/open violations and 1
VLSI Training (Design / verification) Course starting in RajaRajeshwari Nagar, Bangalore. Check the Brochure @ VLSI Training (verification + System Verilog) Brochure Course starting on 18th June 2011. Registrations are open.. Trainers are from Industry... so you get to learn fro
I thought that some examples will be self explanatory: "As opposed with the BFM, the monitor is part of the passive eVC. It is to be used not only in the stand-alone unit level environment, but also in the full-chip verification environment. The monitor uses a scoreboard for data integrity check. It assumes that data at the DUT output will be
...I can't see if there is any error in my design by looking at the .sol and .cmp there any other way? Most PCB design CAD softwares have DRC tools wich allow to detect manufacuring rules violations. Had you performed that verification ? +++
I am vinoth , completed BE- ECE in the year of 2007. I am having 3+ years of experience in the field of FPGA/ASIC -RTL Design and verification. Actually i am looking for FPGA (VLSI) JOBS in outside country like Singapore,uk,usa.If you know any jobs related to above mentioned field kindly inform me mail
I am vinoth , completed BE- ECE in the year of 2007. I am having 3+ years of experience in the field of FPGA/ASIC -RTL Design and verification. Strong knowledge in VHDL and digital electronics. I have been having 3.6 yrs of experience in FPGA (RTL design) field. I am looking for FPGA (RTL) design job. Is there any opening let me know
I have started my career as VLSI Design Engineer and i am trying hard to learn certain things in synthesis and STA. I have created an I2C Slave with the intention that it should support std, fast and HS mode. I have completed coding it in Verilog HDL and have made sanity verification. Now on coming to synthesis part
Hi friends, I have completed my B.E in Electrical & Electronics, 2011 passout. I have done course on VLSI design & verification recently. I am searching for job in VLSI domain. Please let me know if there are any openings in companies in this domain. My email-ID is farhankhan.dec29@gmail.com. Thank You..