Search Engine

Verification Completed

Add Question

1000 Threads found on Verification Completed
I'm trying to erase a PIC16f877 using Picstart plus and mplab 7.20. Selecting Porgrammer -> Erase device does nothing! On selecting read, mplab seems to be reading the memory ( as seen in taskbar on left bottom) but then I get the message : Device is data protected! Data memory may be invalid. Device is code protected! Program memory may
I was involved in ASIC design for four years. In our company, I completed two chips. I took part in system design, write RTL codes, FPGA verification, chip synthesis, pt and so on(The work of post layout is done by foundary). But these days,I am at a loss. I dont know which direction is better in the future. So are there any senior engineer
yes,you can't say verification is completed for design and you can say only that i have done verification of some percentage(%)... the percentages based on your verification strategies. like if you done branch coverage you can say how many branches have you exercised successfully, if you done toggle coverage you can say how (...)
hi all, I completed coding FFT using verilog. I am verifying my output with matlab inbuilt fft operator. As my N (no' of samples are parametrized) for small values of N there no much difference but for N = 512,1024.. some values having difference of +/- 9. I plotted frequency waveforms for my FPGA output and matlab outupt the wave forms are givin
Hi All, I have experience with block simulation in digital design. I wish to learn large system verification including hardware/software co-sim. Could someone give the completed example or book of it ? Thanks a lot. Brs, John
Hi guys, There's a huge calling for verification engineers with a lot of companies in the UK at the moment, they're calling out for engineers with a knowledge of UVM/OVM methodologies at any level, get in touch with me and I can introduce you to some of my contacts.
Hi guys, I'm a B.E(ECE) student passed out in 2012. And also i have finished a VLSI Design/verification course just now. But i could not find any openings in this field. I have also completed 3 projects during the training period. Which includes both Design and verification. Please suggest me some companies for (...)
Hi A Logic verification and Debugging System A Formal Equivalence Verifier for Digital Circuits A Fault Simulation-Based Approach to Design Error Diagnosis 1. -> t tnx
Hi all, Check out this cool tool for verification. . There is short info about the tool in this link, Regards Ezi
Hi All, Can anyone here tell me or give me information about Bus Functional Model in verification methodology. Thanks! rgds, Skynet
Hi, I have a new website where you can find my good old specman tutorial, as well as an interesting blog on verification issues: enjoy and respond, Avidan
about Hardware/Software Co-verification .
Taking Co-verification To the Limit ARM Creates a Virtual Prototype of its Latest Core Running Windows CE
Hi, everyone, I am looking for the formal verification tool, it's said that the verplex is a good tool for the formal verification, who can tell me where I can downloaded the evaluation version software. Thanks I think the only way to get it is ask their sale for product information, as i know, they don't offer eval
vear verification paper
Mixed Signal SOC verification
Whole-Design Formal verification of a 5-Million Gate Design by Equivalence Checking Is Possible with a Small Memory Footprint
Methodology for HW/SW Co-verification in C/C++
Transaction-Based verification in SystemC
The Effects of Hierarchy on Debug time in Formal verification Tools with and without Decompositional verification
See my post: Design verification with E language ebook. ------------- Saho
it is easy to design verification Board by oneself. the ARM's board is simple to integrate FLASH, SDRAM and etc. so refer to some FPGA board such as INSIGHT, you will find it easy to design
Hi Guys, Here is a useful whitepaper on verification.Just check this out... thanks.. Regards, - satya
self checking verification....
Hi Test suite for verification of the verilog Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at 1. -> t tnx
hi all, I have heard a lot about this.. but dont really know what it is and why do we need this tool.... My concept of RTL2GDSII flow 1.specification 2.Design 3.RTL Coding 4. verification 5.Synthesis 6.Test Insertion .... and goes on where in this flow will formal verification come into picture And also what is equivalence checke
A good design process is to have two teams, one that designs the RTL code and one that designs the test cases at the top level (Component interface). Both teams use the hardware specification as a reference. The design team make some validation at the block level to validate the basic functionality and the corner cases that are not
Hi Friends, Iam looking for a quick ramp up on physical verification on Calibre. If any one is having such doc, Can you please share with me. Looking for a positive reply, -Sid
In SoC which use OCP as main on-chip bus: - for block-level verification, you need OCP reusable verification component (eVC if you use Specman ? you could buy it from Vericity or IP suppliers, or BFM in Verilog, VHDL or Vera) to build consistent verification environment for all sub-modules - for top-level verification, if (...)
Do we have anyone in the group who can give some sort of a comparative analysis between the several verification strategies that are on in the industry. I see Vera, SpecMan, SystemVerilog and Jeda all competing in the same space.
IMHO, there are still no good verification tool for mixed signal designs, vcs+nanosim or ams(eldo/mach+modelsim) are not good enough to handle complex mixed signal designs.
e, and you must employ hardware accelerator to increase verification speed.
Hello, Have someone developped a verification environment (e-languege) for the controller area network? I need some inputs to start my own verification env. Thanks for ideas and support. Regards, Firfi
hi, I think the most important is verification plan. and how to estimate functional coverage. and as to tools, I think verilog is not very efficeint, I think maybe you can try systemverilog/systemc/vera/sugar/cycleC., etc. they both are efficeint in simulation and have more power than hdl.
I suggest two books for your reference. 1. Writing testbenches : functional verification of HDL models 2.Principles of verifiable RTL design : a functional coding style supporting verification processes in Verilog
There is a very good book, "SOC verification Methodologies" by Singh , it is in e book upload foroum. You get a hold on SOC verification and s/w h/w co sims.
To so such high speed verification is almost impossible for fpga. Unless you spend extra 2-3 month on it tuning the timing path. generally we can run about 40Mhz on virtex II.
How to verification, not simulation!
I wonder if anyone could recommend a University in NA or Europe which offers good research expertise in IC verification. Or even better, perhaps a Professor's name. many thanks. dram
Use Formal verification & HVL tool.. write test scripts .. download bin file to fpga and test (sometimes) Browsing net (hehe.. just kiddin)
The DFT is more test related, while DFV is more verification related, focus on Functional consideration.
Hi , In my new task , I assigned a task of SOC verification using ALP. Please provide for how to proceed further. Any help is appreciated.
hi, Many simulation tools support this. VCS, NC-Verilog etc. But I think when you do verification, Perl is very good language for dealing the result files. And shell will help you build the automatic test enviornment. For my opinion, PLI is more difficult than perl and shell.
Formal verification cant find your functional bug.
when you do verification, you can use assert to warn the data have error, this can reduce you debug time.
Hi SystemVerilog for Design & verification A good set of Full papers for download. 1. -> t tnx
Hi A Community of verification Professionals (Forum) 1. -> t tnx
No Not synthesis but, doing verification.
Coverification means instruction set simulation plus HDL simulaiton. Mentor's seamless is a good tool for co-verificaiton.