13 Threads found on edaboard.com: Verification Completed
I'm a B.E(ECE) student passed out in 2012. And also i have finished a VLSI Design/verification course just now. But i could not find any openings in this field.
I have also completed 3 projects during the training period. Which includes both Design and verification.
Please suggest me some companies for (...)
EDA Jobs :: 12-11-2013 01:44 :: sreekand :: Replies: 0 :: Views: 434
hi I have completed my M.Tech in VLSI Design from C-DAC, Mohali. I have knowledge about verilog, system verilog, OVM UVM methodologies, AHB\AXI protocols. Is there any opening of VLSI Engineer. Before this i have 2 year exp. in industrial automation(PLC,SCADA). Plz reply what should i do now
EDA Jobs :: 09-25-2013 08:16 :: pandit007 :: Replies: 0 :: Views: 485
I have experience with block simulation in digital design.
I wish to learn large system verification including hardware/software co-sim.
Could someone give the completed example or book of it ?
Thanks a lot.
ASIC Design Methodologies and Tools (Digital) :: 09-24-2013 06:41 :: john7796 :: Replies: 0 :: Views: 185
hi all, I completed coding FFT using verilog. I am verifying my output with matlab inbuilt fft operator. As my N (no' of samples are parametrized) for small values of N there no much difference but for N = 512,1024.. some values having difference of +/- 9. I plotted frequency waveforms for my FPGA output and matlab outupt the wave forms are givin
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-02-2013 06:25 :: achaleus :: Replies: 0 :: Views: 381
I have completed my B.E in Electrical & Electronics, 2011 passout. I have done course on VLSI design & verification recently. I am searching for job in VLSI domain. Please let me know if there are any openings in companies in this domain.
My email-ID is email@example.com.
EDA Jobs :: 12-18-2012 07:59 :: farhan29 :: Replies: 0 :: Views: 512
I have started my career as VLSI Design Engineer and i am trying hard to learn certain things in synthesis and STA. I have created an I2C Slave with the intention that it should support std, fast and HS mode. I have completed coding it in Verilog HDL and have made sanity verification. Now on coming to synthesis part
ASIC Design Methodologies and Tools (Digital) :: 06-20-2012 19:24 :: bhav :: Replies: 4 :: Views: 1171
I am vinoth , completed BE- ECE in the year of 2007. I am having 3+ years of experience in the field of FPGA/ASIC -RTL Design and verification. Strong knowledge in VHDL and digital electronics.
I have been having 3.6 yrs of experience in FPGA (RTL design) field. I am looking for FPGA (RTL) design job. Is there any opening let me know
EDA Jobs :: 12-28-2011 03:32 :: firstname.lastname@example.org :: Replies: 0 :: Views: 639
"verification is never complete " explain in vlsi design context
ASIC Design Methodologies and Tools (Digital) :: 11-01-2011 01:35 :: poornimargowda :: Replies: 1 :: Views: 645
I am vinoth , completed BE- ECE in the year of 2007. I am having 3+ years of experience in the field of FPGA/ASIC -RTL Design and verification.
Actually i am looking for FPGA (VLSI) JOBS in outside country like Singapore,uk,usa.If you know any jobs related to above mentioned field kindly inform me
EDA Jobs :: 10-19-2011 01:08 :: email@example.com :: Replies: 0 :: Views: 708
I am working on a DTMF tutorial on Cadence SOC Encounter 9.1. Since this is my first time i am unable to even decide what to do to remove my errors.
Presently i have completed CTS and verified the design by connections and geometry.
I got almost all of the error after the verification step.
I am getting 20 connectivity/open violations and 1
ASIC Design Methodologies and Tools (Digital) :: 05-04-2011 12:56 :: INS-ANI :: Replies: 0 :: Views: 635
Dear Experts ,
Iam into a designing of core IP and sucessfully completed it using verilog
and functional verification is done using Modelsim se 6.0.
My IP core has 5 main modules of which I synthesized 1 module using xilinx ISE 8.1i demo version
and the gatecount was something around 122k[/col
ASIC Design Methodologies and Tools (Digital) :: 02-14-2008 05:31 :: thakur.umesh :: Replies: 0 :: Views: 527
With a master degree in VLSI design, I can not find a job in a year after I graduated. I do not have any employment experience. During the graduate study, I completed three project design including ASIC and FPGA design from HDL coding to physical verification in DSP, and one is the thesis project. I had six interviews about ASIC/FPGA designer or Ph
EDA Jobs :: 10-13-2006 00:49 :: vickyma :: Replies: 2 :: Views: 1131
I was involved in ASIC design for four years. In our company, I completed two chips. I took part in system design, write RTL codes, FPGA verification, chip synthesis, pt and so on(The work of post layout is done by foundary).
But these days,I am at a loss. I dont know which direction is better in the future.
So are there any senior engineer
ASIC Design Methodologies and Tools (Digital) :: 04-14-2005 09:28 :: sunms :: Replies: 1 :: Views: 785