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33 Threads found on Verilog Ahb
i want to make a design for AMBA 3 ahb-Lite Protocol i have the design for master and slave but i have a problem when i make the test bench the value of the HRDATA is do not care ,on the other hand the slave design return the correct value for HRDATA but the master does not, is there a special method to connect the master and slave together ???
what is the major difference between verilog HDL and VHDL???? Which is best in designing the AMBA ahb, ASB,APB,AXI????? The biggest difference is VHDL's a strongly typed language and is significantly more verbose than verilog. Either language will work well at implementing any if those bus protocols. Both lan
Hi, I am implementing arbiter module for AMBA ahb protocol for real time masters in verilog HDL. I want to know what value should I specify for HCLK signal. And what value should I consider for as my bus speed/bus bandwidth/bus rate? At least suggest me the source from where I can get this information. Waiting for your urgent reply!!!!!!:roll:
Hi, I am implementing arbiter module for AMBA ahb protocol for real time masters in verilog HDL. For that I need to calculate deadline for the real time masters. It will be calculated as: Deadline = Execution time + Arrival time of request + slack(assumed). Hence I need to know the amount of data the master is going to read or write for calc
Hi; I am implementing arbiter module for AMBA ahb protocol in verilog HDL. For that I am considering real time masters having constraints in terms of deadline and service cycle. Now I am stuck at a point and want to know how the master convey this constraints to arbiter so that the arbiter will do the scheduling and grant the bus to one of the
Given this is the block doesn't appear to be a GPIO interface from the ARM so you'll have to write some HDL (verilog/VHDL) to interface the ahb bus to a set of GPIO pins from the Versatile fabr
Hello, I am studying ahb and want to implement a simple ahb2APB bridge without split/retry, I have 2 modules inside my bridge 1. ahb Slave + Address decoder and 2. the state machine for APB. i have no clue how to start with the ahb slave and what functionality to implement. it is a single master bridge so i wont be using (...)
hi I have completed my M.Tech in VLSI Design from C-DAC, Mohali. I have knowledge about verilog, system verilog, OVM UVM methodologies, ahb\AXI protocols. Is there any opening of VLSI Engineer. Before this i have 2 year exp. in industrial automation(PLC,SCADA). Plz reply what should i do now
I don't know anything about ahb, but I think you've got two different serial protocols, right? But you're writing something in verilog; is there an FPGA or CPLD in here somewhere? If you ARE, in fact, using an FPGA, the simplest solution would be to use a fifo between the two clock domains. I think we need more information.
using verilog u can do it by writing testbench u can do
hi i have done with random control and address generation for my AMBA ahb project also i have applied it to master and have taken two separate output file(1 giving input to slave 2. taking output from slave) problem is that i have to compare both file manually. A i m thinking for comparator logic which will automatic check for error. please gui
RTL is register transfer level, it is the VHDL/verilog code of your design. Thanks.
Hi All, I have have a doubt reg the timing parameters available in the protocols like AMBA ahb, AXI etc. My question is: what is the use of the timing parameters provided in the spec? 2. As a designer how we should interpret it and while coding the protocol using verilog HDl, what is the exact place where we should use it? pl explain me the conc
hi all i want to interface PCI with ahb me out in finding a verilog code for ahb to PCI bridge
Hi friends, I have been working very very hard for the past few days on the arbiter part of the amba ahb bus architecture. I am using a fixed priority algorithm for allocating grant to the bus master. I tried simulating the arbiter verilog code on modelsim with the testbench that I wrote. I was very disappointed. :cry: Even a simple grant signal
You can generate a default testbench using the following free testbench generator tool- Free verilog Testbench Generator in Java
I am working a design with ARM. Does anyone has the RTL code of ARM ahb-to-APB bridge? Help me, please. Thanks.
Hi, I am doing a project that needs amba ahb/apb buses, including master/slave/arbiter interfaces.... Is there any open verilog to refer to? I know sonics provides an evaluation version, but the code is encrypted... thx, bruce
Hi all.. I am doin the project namely " AMBA ahb protocol checker with efficient debugging mechanism " i need verilog code for this.. anyone pls fwd me.. thankyou
Hi Friends, I Started to design ahb protocol , but still i am little confused with concepts, can anyone provide me any reference code for ahb either in VHDL or verilog, This will be more helpfull to me. Thanks and Regards Kanimozhi.M
hi frndz... I want to test a few things in VHDL. Can any1 suggest me any site where i can find complex VHDL/verilog codes using more than 1 clock signal in the design. thank you
i need the bfms to build the testbench, is there anyone who can provide the bfms in verilog?
Hi all........ i have gone through but could not find the Code for ahb in verilog... Anybody Having ahb Code in verilog....PLZ Thanks
hello group, Please give me clear idea regarding Monitor and checker fo ahb.Examples,pdf's welcome.Its urgent.thank you
Hi all how do i write a wrapper to interface a fifo to ahb. i have the fifo signals namely fifo_data fifo_reset; fifo_clk; fifo_full; fifo_empty the fifo code is in verilog. :idea: thanks in advance regards srinivas
i am doing a project on AMBA-ahb interface with the referance AMBA specification 2.0 from ARM.can any body help me to get the source in vhdl/verilog. Hi, If you want a ahb Master verilog Model, i can provide it to you! My group has utilized to debug the whole system! Now, the hardware verification has reached an end. a
I'm working with ARM7 core and need an APB to ahb bridge. Where can I find this block in verilog or vhdl? thx
how to design a memory controller for sdram(micron MT48LC2M32B2) using AMBA ahb... wat r the basic modules required... what would be the operation of each module... the coding should be done in verilog . looking forward for a faster response from anybody..pls If u r looking for a useful or even faster response.. You should
Suppose u have only 2 masters and an arbiter... when 2 masters requests for bus simultaneously .. which one do u wanna give grant signal.. write that in verilog and synthesise. to get a simple arbiter
Anyone have the VHDL /verilog Code for Amba ahb master/slave interface thanks smartkid
Anyone has ABMA ahb/APB Bus Functional Model (BFM), verilog or VHDL code or samples? I'd appreciate any samples, code, or documents other than the ARM's spec.
I want verilog code of APB, can someone help me?