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238 Threads found on Verilog Analog
Is it also possible to get the output as voltage?No. Can you uderstand verilog-D surely ? Can you understand Available data types are "wire", "reg", "real", "integer". And you can not use "real" and "integer" as ports. Simulator for verilog-D is classified a
Cadence Spectre can not accept verilog-D. You have to use NCSim with AMS option which is called as AMS Designer. Or legacy VerMix(=spectreverilog) which is a cosimulation between Spectre and verilog-XL might be available.
Dear all, i want to generate 1MHz, 2MHz, 3MHz square wave in a parallel manner. and i want to increase or decrease the voltage and frequency for individual square how to design in verilog. hi, you can produce n number of square waves using your clock..for that, what is your clock frequency and you can
Schematic to layout (given a suitably constructed primitives library) is offered (some assembly required). Code to layout, I have never seen in the analog realm. Structural verilog / veriloga (where every element at the lowest level is a real component, transistor / resistor / capacitor, call and no "loop" or such constructs, might be (...)
Are you sure you aren't talking about verilogA, which is not the same as verilog (A digital hardware description language). If you are discussing verilogA you posted this in the wrong section. As this the "Digital Design and Embedded Programming => PLD, SPLD, GAL, CPLD, FPGA Design"
Hi, I'm running verilog-a for the first time and trying to get the following code to work: analog begin if (sIntegral > 0) integrand = V(bj); else integrand = 0; sIntegral = idt(integrand,.5); $fstrobe(fprt,"%f", integrand); $fstrobe(fprt,"%f", sIntegral); etc..... The behavior I want to see i
analog circuits are designed by drawing schematics and usually simulated with SPICE based simulators. verilog-A is suitable for the description of certain mixed signal circuits, not generally for analog design.
What about verilog? What it is? verilog is for digital circuits.
Hello, I am using AMS to try mixed signal simulation with two inverters: one is in analog with nmos/pmos, the other is in verilog with "assign out =~in;", and the analog inverter will drive the digital one. The plot is not very precise as expected that the digital output didn't rise or fall corresponding to the vthi/ vtlo. 125
"analogLib/switch" is netlisted as Spectre primitive "relay". See result of "spectre -h relay". Instantiate relay outside analog begin ... end block in verilog-A. You can see example of instatiation of Spectre Primitive in verilog-A in "rfLib/osc". Here Spectre primitive, isource is instantiated in (...)
i need to synthesize verilog analog file of comparator to finally get transistor level netlist, can anyone help me, if it can be done by files provided by ncsu would be better as i have done my earlier work by ncsu provided lib files. keenly waiting for any reply and thank you in advance
hi, I am new user of cadence incisive unified simulator. I want to run a mixed signal simulation. I am able to run a mixed signal simulation of a design consisting of a verilog module and an analog schematic module, when using cells only from analogLib in the schematic. The problem is when I use the cell from the foundry library there are (...)
Hi, I want to build a SAR ADC. I am starting from behavioral level. The comparator is described in verilogA and the SAR logic in verilog. Can I use spectre simulator for that or do I need another simulator environment for that? thanks a lot for helping
Hi, I have a requirement to define an output with a more 'analog' feel then the straight forward digital definition that I currently have in place. dac_out is defined as a digital output This is simply 1 or 0 based on: ------ module DAC (IOUTN, IOUTP, VDDA1V8,, BIAS, CLK, DAC, ); inout VDDA1V8;
That sounds like a pretty ambitious first project for an FPGA, are you sure that's what you want to do? You need to learn the details of the particular FPGA itself, verilog or VHDL, video (analog and processing algorithms), Vivado, analog/digital-digital/analog conversion, DSP, etc. The fact that you don't even know how to (...)
Hi, I use SMASH for a couple of simple verilog-AMS codes. Although it works for both analog or digital module, I do not see any interconnection in its example projects. I download an interconnection project, which was originally for Cadence EDA tool. The project does not show the expected behavior in SMASH transient simulation. Do you know ho
Hi, I use SMASH to learn verilog-AMS. I find that when I instantiate a sine wave generator only in SMASH, it can generate sine wave as I expect. When I add another module, no matter digital or analog, the sine wave output has only very small peak value noise (The names of sine module and amp module are different. Thus they are not shorted?).
Hi, I see the below code from verilog-AMS reference book. `include "disciplines.vams" module a2d(dnet1a, anet); input dnet1a; output anet; wire dnet1a; ddiscrete dnet1a; electrical anet; real avar; analog begin if (dnet1a === 1'b1) avar = 5; else if (dnet1a ===
Hi, There is a PLL verilog-AMS model. Now it works in the simulation with sine input signal, i.e. the output sine phase tracking input signal source phase. I would like to see what output will be for a square wave input. I know that a large magnitude sine wave passing a limiter will be a square wave. Yes, I can code it with several line code. Ar
is there any possible to give analog input in MODELSIM. i need to design analog vco using verilog. i wrote transistor level coding , but its not working. please guide me how to proceed. I believe you'll have to write your code in verilog-AMS. Check out
I think it si mostly used used for Mixed verilog and VHDL simulation, but not as popular as its mentor conterpart
hi there, I'm pretty new to ADS and verilog-A (Version 2012 here!!!). I'm trying to build a custom model (starting with the most simple example of a resistor). I know how to write the code and have a basic knowledge of setting up simulations in ADS. I went through all the tutorials and ADS help to get an understanding of the structure of the A
Hi All, I am using verilog A model ofTFET from Penn State University which is given below. `include "constants.vams" `include "disciplines.vams" module NTFET(d,g,s); inout d,g,s; electrical g,d,s; real Ids, Cgs, Cgd, Qs, Qd,Qg; parameter real W=1; //Device width analog begin Ids=$table_model(V(d,s), (V(g,s)), "IdVg-NTFE
Hi, I'm running a mixed mode design that is using verilog for digital and spice netlist for analog. The tool is using ncverilog. I'm wondering that I can't see any response from the analog design on the waveform that is in a fsdb file. Is is a problem on fsdb dump? Suppose, the dump systemtask $fsdbdump is the same (...)
Dear Sir, I'm running a co-sim by using hsim & ncverilog. analog circuit is written in spice netlist. And digital circuit is in verilog. After running, some error message found as below. Error: parameter "pwr" not found for instance xsdi_rx_top.xtenbit_sdi_rx_topall.xtenbit_sdi_rx_top.xrx_sdi.xrxpll_yx_sdi.xlcvco_sdi_rx.xi18 (...)
i am going to design digital block. This block is part of mixed circuit. Then, digital part is designed by verilog and analog part is designed by cadence. i have 1 problem. my design block don't use pad because digital block and analog block is combined by cadence virtuso. i found the some icc design flows but this design flows have case (...)
hai there, I have write verilog code to convert analog signal to digital for a sin waveform of 100khz. attached with this message is the output data that i plot on excel file. can you please explain to me the results that i obtained...i cannot understand the results that i get..thank you.. 105908
Hi, I am now working on a AMS verification using irun. I have an analog module (verilog-AMS model, .vams) and a logic module (Systemverilog RTL netlist, .sv) and want to integrate them together for system verification, especially on the control of the analog module by the logic one. The testbench I am using is in .vams (...)
Many times analog circuits are modeled in verilog. How? verilog has no specific means to model analog circuits. Digital circuits with analog interface and the analog enviroment can be modelled in testbenches to a certain extent.
I've tried this and found the created schematic a nearly useless, unreadable mess. Now, I do not see verilog (different than veriloga) in your view-list. But an analog simulator is not going to switch into digital views usefully anyway. The mixed signal setup involves partitioning and somebody somewhere has to insert all of the (...)
Questa-ADMS can simulate verilog-A. It is an extension to Modelsim.
Dears, i have external clock frequancy of 40 Mhz in xc9572xl CPLD device ,i am very new for verilog can anyone answer me for phase lock loop for obtain Fcco (output core clock frequency ) 120 MHz .how can i write coding for that? thank you very much for all visitors and replys
You should tell in which language/syntax you need the description. Simulation languages like (H)SPICE, SPECTRE, ..., analog description language like verilog-A or aVHDL, or other mathematical description language like MATLAB, or pure mathematical description? Or anything else?
Hi, There is a verilog (in the context it may be referred as verilog-D) to model digital processes, there is verilog-A to model analog processes. verilog-AMS allows modeling both analog and digital processes in the same module. You can consider that verilog-D and (...)
hi all i have chosen zigbee transmitter as my masters project and am going to implement it in verilog so guys i want to know that what are the related topics i have to study in order to implement the zigbee transmitter, so i have bit to symbol block in the zigbee block diagram so in order to implement this block what subject should i read please he
For example If i have generate an analog signal of Asin(2*pi*f*t) How can i read that signal using verilog : please clarify
Hi, I am trying to write a verilog A model for Voltage controlled current source. module VCCS(p,n,pc,nc); inout p,n; input pc,nc; electrical p,n,pc,nc; parameter real gain=1; branch (p,n) iSrc; analog begin I(iSrc) <+ gain*V(pc,nc); end endmodule It works fine when there is a load connected to the current sourc
ViaDesigner includes: Schematic capture, SPICE modeling, VHDL entry, verilog entry, VHDL-AMS (analog & mixed-signal) modeling and all of these design entry methods can be combined in a unified simulation environment. Not free but on $169 for a 1-year license. Free 30-day trial available at
Hi people I have been trying to implement the following code which is a current mode comparator into mentor graphics ADMS tool; I have been receiving the following error: analog DC computation aborted : no DC convergence found in this design Is there any problem with my code ? The schematic is also attached. `include "disciplines.h" module
There is no <+ operator in verilog
Hello sdedov I want to store the timing instant at which the output is being stored, how to get this in verilog-A and $abstime stores values as "0.00000001,0.00000001,0.00000001,0.00000002,0.00000002 and so on", so no difference in first three values, how to get better precision i.e. let say time is 0.00001231,0.
Is there a way to simulate a digital to analog converter in ModelSim????? I have my verilog code that produces the 16 bit input to a DAC . It would be really nice if I could somehow see the analog waveform in simulation...
Hi everyone, I want to simulate the effect of mismatch and process variation on the system performance of my SAR analog to Digital Converter. The system now is simply ideal system with only one transistor level block, the other blocks are written in verilog-A code in Cadence-Spectre. The easiest way to simulate the mismatch and process v
Hi all, I am trying to simulate an ADC on verilog-A, using MOSFET models generated from TCAD tools. In order to quantify ADC performance in terms of SNR etc. I need to include noise in my simulations too. Can someone help to identify where I can include noise sources in the simulation process and how to include th
Hi, I am fresher in Electronics & Communication Engineering with excellent academic record. I have theoretical knowledge of digital circuits, analog devices and circuits, digital signal processing, CMOS VLSI. I also know verilog HDL and VHDL. I am looking for an entry level front end design job in Bangalore, India. I would appreciate any suggestio
Hi, Does anyone have a copy of the Cadence "analog Modeling with verilog-A" training manual from Cadence? :) Thank U!
In analysis->Tran->Option->SkipDC->Yes Now, it oscillate without sim errors. I'm not using verilog-A, thus I didn't answer to the thread. But it's essentially the same as in any SPICE based analog simulator. You need an initial condition different from steady state to start an oscillator simulation. Skipping initial DC analysis is
Hii friends.... Can we include analog logic in digital logic in the same program in verilog programming..??
Hi guys; I'm not sure if this is the proper place to post this thread; I'm currently simulating a mixed-signal system design by AMS, with analog part drawed in cadence composer and digital in verilog; When it comes to all-corner simulation, AMS is too time and license costly, so I attempt other simulator such as Finesim plus (...)
The question is very unclear (with a light smell of confusion). FPGAs are programmable digital logic devices. Which noise signal do you want to process with your FPGA board? Are you talking about digital signal processing? If so, which analog-to-digital conversion capability is provided by your board? Thanks FvM for re