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Verilog Assign Buffer

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2 Threads found on edaboard.com: Verilog Assign Buffer
Hello all, I am working on a project where I have a SRAM chip which I wrote a very simple SRAM memory controller. I was having a lot of trouble with the bidirectional port and I ended up using a primitive to accomplish the tristating. I used ALTIOBUF and everything seemed fine. I used the module in an instance of another module just to test i
to remove assign statements from verilog netlist