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Verilog Case Statements

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Hi all, is there anyway I can group certain condition together when using case statements? such as case input_vector IS WHEN "001" AND "010" => blah blah.. The above command doesn't work, coz the compiler ANDed the 001 and 010 together, instead of treating them as seperate conditions. Thanks for help!
can anyone explain how if and case statements infer logic after synthesis ?
I have a following code module test(clk,out1,out2) input clk; output out1,out2; reg out1,out2; reg next_state; parameter ONE = 2'b00, TWO = 2'b01, THREE = 2'b10, FOUR = 2'b11; paramter ON = 0, OFF = 1; al
Design a barrel shifter for 16 bit words in VHDL. This barrel shifter is capable of logical shifting input toward left and right direction. Two different architecture designs of the same barrel shifter must be implemented and tested with the testbench you also need to develop. One architecture (e.g., structural) must use a 16-bit multiplexer (M
Gud eveng, I'm getting this error again and again. It's annoying when i try to do further coding. Need some tips while writing synthesizable if/ case statements in detail.
A 4-1 mux written in verilog case statement will be implemented in hardware as .....? A 4-1 mux written using if else statements in verilog will be implemented in hardware as ...? My question is both hardware implementation is same or different? pls explain elaborately......
If you can use Systemverilog, this is quite easy because testbenches are written using dynamically constructed classes and you can read command line switches to help you select which classes to construct. The object-oriented nature of classes makes it possible to switch one class for another at many different levels of the testbench without having
twocmplement and mul_unsigned don't exist in the verilog language. Why don't you simply let the compiler do the hard work for you? (assumes verilog 2001) reg signed a=123, b=-77; wire signed y = a * b; Gives result -9471
if we use a 1)if and else if statement in verilog for generating a multiplexer and synthesize the code what will be the output looks like.. will it be a priority encoder or a Mux. 2) Do we need to declare the output of a assignment statement as wire incase of a combinational circuit 3) Do we need to declare the output of a assignmen
In actual usage you may use an if condion without satisfiying all the possible combinations of the condition for example you want to implement if a=1 set output=1 otherwise output=0 possible verilog codes for this using if statement by a naive user if (a==1) begin
Hi im also planning to learn SYSTEM verilog please send me some file it would help me lot to
anyone having any idea of doing /using sorting algorithm in verilog .... i have used it using comparators but it is taking big logic... kindly suggest any methods.. Thanks
i wonder if the case statement without the parallel directive,is it synthesized to a priority case? and if a full case directive, is it also synthesized to a priority case? is there a way to make the synthesizer to synthesize the code into parallel case without any directive in the (...)
i designed a state machine,when proeceeing the design ,the RTL of state machine is correct. BUT,when i generate its symbol,and conenct it in the top entity,the RTL state machine is not same as the sub_module, and generate the warning Warning (10272): verilog HDL case Statement warning at controlflat.v(112): case item expression covers a (...)
look into the following are a couple of papers at Added after 1 minutes: also came across this
hi lads and happy holidays I am trying to implement a routine, basic code on a fpga with verilog. this will simply perform some calculations, adc/math operands etc to alter the supply voltage. I am doing this to simply have control over the power usage of the fpga. also I would like to have an additional bus for monitoring the power usa
Hi all, I want to write a configurable verilog code of case statement....please help me, if any idea... Example_1: In this simple example, i know how many case expressions may exist in my case loop...4: parameter COUNT_WIDTH = 4 case (COUNT_WIDTH) 4'b0001: something; 4'b0010: something; (...)
The delay syntax is correct, as far as I'm aware of, but you are using continuous assignments in the wrong place (inside a case construct). I fear, you also misunderstood the purpose of verilog iteration loops. They are not generating a sequence in time. Consult your verilog text book in this regard, or ask the guy who issued the (...)
You can use case statements to generate packets in RTL verilog or VHDL. You can find many examples over the internet. A sample is here verilog case statement to generate packets in a Testbench.
Dear all, As lots of books talk about inferring latches in hardware, when we miss few statements during coding like 1- not including else with if 2- not including default case with case statements.... but upon reading XST user manual examples I observed above are missings they not considered both of the above (...)
hello,when I compiled the program ,I face with this warning , how can I remove this warning? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.my_package.all; entity Find_Min_Values_one_rowis port(sum:in int;clk_external,clk,reset:in bit;--L:in matrix1xN; out_min_1,out_min_2:in int;index_min:in bit_vector(2 downto 0);sign_value:in
Hi all, I have a simple question about the case statement in verilog. Is there anyway to write something similar to this VHDL code: case state_reg is when (N-1) downto (0) => .... where N is parameter. What I need is to map the cases in verilog let say from N-1 to 0 to one logic expression. (...)
Hi, I was just wondering something. If i have a some code like this: process(CLK) begin case Signal is when Signalcase1 => Signal <= Signalcase2; when Signalcase2 => Signal <= Signalcase3; when Signalcase3 => null; end case; end process; Now what (...)
just do me another favour just give me starting tips.. starting logic code... remaing i will do it by myself.. In your case I would start with a VHDL book first. Most of them cover logical equations and more advanced code writing. As already pointed out "case" statements are the most preferred way. Or see it as an address de
in c is there any difference between the if and the case statements?
I know that the switch case statements synthesize to Multiplexers. What do 'If-Else' or 'If-ElseIf' statements synthesize to? Thank you.
Is is proper coding convention to use a case statement inside an always @posedge clk block? . Something like always @(posedge clk or negedge rst_n) if (rst_n == 1'b0) else case < case variable > . . . endcase It works all right, but I (...)
Hi, there I am very new to verilog-A field, so bear this simple question. I am runing Ken's sample and hold example and got the error like below: Error found by spectre during AHDL read-in. "sh.va", line 5: "'<<--? include "discipline.h"" "sh.va", line 5: Error: syntax error "sh.va", line 11: "electrical Pin,<<--?
hello, I have some basic question and reading different tutorials didn't help. I want to make a state machine that goes though all states a fixed numer of (let's say five) times then stops and waits until a button is pressed. I tried coding this in verilog and also in vhdl. no results. In order to test if the state machine was working i connect
All, I have a question on the "default" branch in a verilog case statement. Notice that the following case statement features all outcomes for the case variable "encoded_signal". There is also a default statement. always @ (encoded_signal) begin case(encoded_signal) 3'b000: (...)
I had to cope with the same but with a smaller DUT. At that time I could not find any free tool to do the job. The verilog contained many arrays: wire regf_time_stamp_cnt_q; wire regf_time_stamp_cnt_d; wire regf_sr_ts_q; reg regf_sr_ts_d; and long case statem
hii i have some query about switch case in C case 'C': case 'c': switch (*comm++) { case 'S': case 's': command = STATUS; break; } break; Tell me why it is necessry to use this switch case format like C,c,S,s? is ther any concept behind this (...)
I am Designing a Instruction decoder 12 bit to 15 bit ..using case statement total 4096 statements .Earlier I used casex so that only few statements need to written .Will it be good to do with case earlier the code was like this casex(op) 35 cases default (...)
What exactly are you trying to encode and decode? Do you just want to, say, connect three switches as inputs, and use the eight LEDs as outputs? I don't see any particular problem with your code (does it synthesise? does it work?) though I find the verilog case statement easier to read.
Hey, I was looking to implement different statements at every rising edge of a clock. I can think of using a counter, incrementing at every rising edge of the clock and assigning different statements at every counter value using case statements. Any better logic for better realization ? Process (clk) (...)
verilog's case statement is an if-else style. this allows odd constructs like "case 1'b1" which can have cases that correspond to expressions. Synthesizers support "parallel-case" and "full-case" for verilog, which tell the tools that the cases are (...)
Dear iVenky, when you are modeling hardware, you can write code in different ways, independent on the HDL you are using (i.e., either VHDL or verilog). Behavioral modeling refers to a way to write code (more precisely, to model your hardware design) based on its functionality: it's like writing the algorithm that solves your problem. With structu
79612 I have to make this in verilog,it`s a project for college. I wasn`t as his classes,because i`m working,and i have no clue how to do it, and no time to do it. He explained me in the picture what i have to do. I have to make an 8biti ALU ,that has to do + on bit, - on bit, AND, OR, negation a on bit... Sorry for my
Hmmm, Google seems to produce a lot of useful results when you search for: "verilog fsm coding styles"
You can't display a 8-bit binary value (0-127) on two (2) 7-segs. You need prof is wrong. That, or there is the ever popular error in translation. 8-bit value displayed on two 7 segment displays should be no problem. T
Can I use IF and case statements in pspice while writing the netlist . If so how do i use it?
hi all what is look up table......how can i use it in vhdl reduce a "case statements"........................ thanks for your help
Hi, Why is it that PICBasic 2.33 cannot cannot hand SELECT..case statements and it cannot handle PIC16F628A only PIC16F628?
verilog "initial" statements are fundamentally synthesizable, but a particular tool may not support it for practical reasons. Some FPGA tools support it. I'm guessing that ASIC tools generally don't support it due to some sort of difficulty with automatically instantiating a power-up reset circuit, but that's just my guess. Yes, you can p
Hi, I am facing some slack problem while synthesis of my RTL. I tried optimizing but not to much effect. Can anyone tell from where I can get some insight of various optimization techniques for improving delay in combinational blocks. Thanks elec
Its an Equality operator.. VHDL Equality = is equivalent to verilog case (identity) equality ===.......
Hello! My design is a large parallel processing unit, which requires to find the bit-length of signed numbers and dynamic shifting in a single cycle Here is my code.. Are there any more efficient/fast methods to accomplish these two tasks? My clock cycle is stingent, and many nested ifs or long case statements might cause timing iss
Dear all, does exist a procedure to convert implicit FSMDs (based on wait statements) to explicit FSMDs (based on switch-case statements)? For example i1 i2 i3 wait(clock = 1) i4 i5 i6 wait(clock = 1) i7 i8 has to be converted in state := A if (clock = 1) then switch (state) case A: i1
Hi, i have implemented a memory of 16*64 i need 2 shift the values i did it by using case statements sme line are as follow case (addr) 64'd59: begin mem <= `D dinput; mem <= `D mem; mem <= `D mem; mem <= `D mem; mem <= `D mem;