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Verilog Case Statements

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48 Threads found on edaboard.com: Verilog Case Statements
I have a following code module test(clk,out1,out2) input clk; output out1,out2; reg out1,out2; reg next_state; parameter ONE = 2'b00, TWO = 2'b01, THREE = 2'b10, FOUR = 2'b11; paramter ON = 0, OFF = 1; al
twocmplement and mul_unsigned don't exist in the verilog language. Why don't you simply let the compiler do the hard work for you? (assumes verilog 2001) reg signed a=123, b=-77; wire signed y = a * b; Gives result -9471
In actual usage you may use an if condion without satisfiying all the possible combinations of the condition for example you want to implement if a=1 set output=1 otherwise output=0 possible verilog codes for this using if statement by a naive user if (a==1) begin
Hello freinds I am learning system verilog. I am following system verilog for design by chris spear. I didnt understand the concept of two important constructs. UNIQUE and PRIORITY. I want a indepth discussion on those. Your help is appreciated Thanks and Regards Deepak
anyone having any idea of doing /using sorting algorithm in verilog .... i have used it using comparators but it is taking big logic... kindly suggest any methods.. Thanks
A 4-1 mux written in verilog case statement will be implemented in hardware as .....? A 4-1 mux written using if else statements in verilog will be implemented in hardware as ...? My question is both hardware implementation is same or different? pls explain elaborately......
i designed a state machine,when proeceeing the design ,the RTL of state machine is correct. BUT,when i generate its symbol,and conenct it in the top entity,the RTL state machine is not same as the sub_module, and generate the warning Warning (10272): verilog HDL case Statement warning at controlflat.v(112): case item expression covers a (...)
look into the following are a couple of papers at Added after 1 minutes: also came across this
hi lads and happy holidays I am trying to implement a routine, basic code on a fpga with verilog. this will simply perform some calculations, adc/math operands etc to alter the supply voltage. I am doing this to simply have control over the power usage of the fpga. also I would like to have an additional bus for monitoring the power usa
Hi all, I want to write a configurable verilog code of case statement....please help me, if any idea... Example_1: In this simple example, i know how many case expressions may exist in my case loop...4: parameter COUNT_WIDTH = 4 case (COUNT_WIDTH) 4'b0001: something; 4'b0010: something; (...)
The delay syntax is correct, as far as I'm aware of, but you are using continuous assignments in the wrong place (inside a case construct). I fear, you also misunderstood the purpose of verilog iteration loops. They are not generating a sequence in time. Consult your verilog text book in this regard, or ask the guy who issued the (...)
You can use case statements to generate packets in RTL verilog or VHDL. You can find many examples over the internet. A sample is here verilog case statement to generate packets in a Testbench.
Dear all, As lots of books talk about inferring latches in hardware, when we miss few statements during coding like 1- not including else with if 2- not including default case with case statements.... but upon reading XST user manual examples I observed above are missings they not considered both of the above (...)
If you can use Systemverilog, this is quite easy because testbenches are written using dynamically constructed classes and you can read command line switches to help you select which classes to construct. The object-oriented nature of classes makes it possible to switch one class for another at many different levels of the testbench without having
just do me another favour just give me starting tips.. starting logic code... remaing i will do it by myself.. In your case I would start with a VHDL book first. Most of them cover logical equations and more advanced code writing. As already pointed out "case" statements are the most preferred way. Or see it as an address de
hello :-) I'd like to compare a 8 bit address value with a 8 bit mask that contains x bits. Comparison works with casex. Then I am trying to do it with: wb_addr_i == address_wd2 where wb_addr_i can be from 8'hE8 to 8'hEF and address_wd2 is 8'b11101xxx That code fails, I tried with === but it also fails. Does anyone knows which o
. Design a 4:1 mux in verilog. Multiple styles of coding. e.g. Using if-else statements if(sel_1 == 0 && sel_0 == 0) output = I0; else if(sel_1 == 0 && sel_0 == 1) output = I1; else if(sel_1 == 1 && sel_0 == 0) output = I2; else if(sel_1 == 1 && sel_0 == 1) output = I3; Using case statement case (...)
where can i find stuf on verilog (in the net)?
Hi i had a question in verilog in an interview. ie.. if u r using nested if-else statements in your code and u find some timing problems. In that case how will u change your code (problem is with the nested if-else). Plz get me the solution.. haran
always(*) is not an error accoding to verilog 2001 std. assgn a=b; will take more simulation time than always(*) a=b; where a has to be of type reg as pointed out by Echo! For more information please refer to ncsim simulation guide.
This is independent to simulators. The timing model should be defined by in verilog. This question is simply about the concept of concurrency and sequential structure. All statements inside a always or initial block are processed sequentially and you can only see the final result. That means a = 0.
Can any body tell me which is better in Initial Statement in verilog Blocking or Non Blocking also in Task which is better.
Basically, it's rather a question of RTL design than a verilog specific matter, I think. I used the negative edge because qu(at)rtus indicates that the rom will clock the data out on the positive edge In this case posedge would be the usual solution. In a synchronous design, data are safely transfered between registers clocked at th
hello, I have some basic question and reading different tutorials didn't help. I want to make a state machine that goes though all states a fixed numer of (let's say five) times then stops and waits until a button is pressed. I tried coding this in verilog and also in vhdl. no results. In order to test if the state machine was working i connect
Hi guys, would be very appreciative of any help anyone can give. I'm trying to design a 5bit binary to thermometer decoder for use in a 10bit segmented current DAC. //verilog HDL for "lablib", "ee435" "behavioral" module ee435 (bin, thermometer); input bin; reg breg; always @ (bin) begin breg = bin; case (breg) 5'b000
i tried using tat too...but in vain.... i also tried using assign-deasign statements & also force-release(4 simulation purpose alone) too...but didnt work.... as of wat i heard frm a verilog expert.. he says tat i cannot use module instantiation inside an always statemnt.... but i do not know how to execute a code which using differen
Hello, I'm trying to implement a voltage controlled capacitor in verilog-A. I tried to use the following script: `include "disciplines.vams" `include "constants.vams" module capacitor(p,n); inout p,n; electrical p,n; analog begin if(V(p,n)>=0 && V(p,n)<2.5) I(p,n) <+ ddt(V(p,n)); else I(p,n) <+ 0.1*ddt(
I had to cope with the same but with a smaller DUT. At that time I could not find any free tool to do the job. The verilog contained many arrays: wire regf_time_stamp_cnt_q; wire regf_time_stamp_cnt_d; wire regf_sr_ts_q; reg regf_sr_ts_d; and long case statem
for second question answer is x first question is more complicated.. first is you will never need such thing during your paractical rtl second is there is a very simple rule of blocking and non-blocking... use blocking assignments for synthesizable combinational verilog constructs and use non-blocking when making sequential circuit
Hi, I am a verification guy and want to know if following verilog codes are valid or not: 1) always @( a & b) 2) always @(a || b) 3) always @(a && b) 4) always @(a | b) Thanks
Hey all, I'm very new to programming for FPGA boards so I'm pretty lost. I'm using a Spartan 3 board and developing in verilog using Xilinx ISE. I have a bunch of warnings in my code like the following: WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not (...)
if(key0==1) begin adder add0(most, least, result); end else if There are several basic violations of verilog rules in this few lines. - "if" statements aren't allowed in concurrent code, only inside sequential blocks. - module instantiations have to be unconditionally - module instantiations must be place
That depends on whether you a re talking about combinatorial or sequential logic, and how complete your non-default case branch statements are. For combinatorial logic, you need to make sure that variables you are writing to are assigned at least once given every possible path through your process. If there are unspecified case branches, and (...)
Hi, I need a help in writing a verilog code for some signals like CLK, CKE, and RESET with their delays. I have written the code according to my knowledge but there are some conflictions in that. Iam here attatching the related document along with my code please check it out and suggest me. thank
77204 could any one explain slid above slid? please...
Dear iVenky, when you are modeling hardware, you can write code in different ways, independent on the HDL you are using (i.e., either VHDL or verilog). Behavioral modeling refers to a way to write code (more precisely, to model your hardware design) based on its functionality: it's like writing the algorithm that solves your problem. With structu
79612 I have to make this in verilog,it`s a project for college. I wasn`t as his classes,because i`m working,and i have no clue how to do it, and no time to do it. He explained me in the picture what i have to do. I have to make an 8biti ALU ,that has to do + on bit, - on bit, AND, OR, negation a on bit... Sorry for my
Hmmm, Google seems to produce a lot of useful results when you search for: "verilog fsm coding styles"
Yeah. I did follow the syntax. I m generating a set of 75 values in a module and i m trying to pass it to another module where the conditional assignments are needed. this is a piece of my code. always @(m1,kk01,kk02,kk03,kk11,kk12,kk13,kk21,kk22,kk23,kk31,kk32,kk33,kk41,kk42,kk43,kk51,kk52,kk53,kk61,kk62,kk63,kk71,kk72,kk73, kk81,kk82,kk83,kk
Hello guys, I want to instantiate a 250:1 MUX and connect a 250bits bit vector to the input of the MUX in verilog. The instantiation statement would be like: my_mux u( .input1 (in), .input2 (in), .input3 (in), .... .input250 (in) ); The question is instead of manually connect each port and repeat 250 times
Hi all, Can you please help me to clear the following warnings.... WARNIG:Xst:737 - Found 1-bit latch for signal <$old_fsm/1/fsm_enable_misr_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 -
Hello I am learning PERL programming and I have been using verilog for a while now, I am still unable to learn on how to write a PERL script for RTL level design. Any insight on this would be helpful.
paths on SDF should match your verilog model's specify block. you can try generating SDF without conditional path in case your specify block does not have COND statements.
cant you write a vhdl or verilog code for the same??
Hello, I need to write a script which will transfer specific module/s in the verilog design from one place in the hierarchy into another. The problem occurs when I face design with ifdef and generate->case/if statements. I know this could be done, but this is a hard work, so I want to be sure that I won't reinvent the wheel. Maybe (...)
But my question is why tool is not taking a precidence like what it does for two variables. Anyway as its non blocking and blocking , it wont be assigning at the same time. in verilog all the statements are executed at same time, that's the main special feature of that..here in your example you are using blocking an
Hi, I've been having this doubt for a long time, but just thought of asking out. I've been using functions\procedures so far only for combo circuits such as complex adder\mult, muxer, etc. However I've always wondered why not use clock based seq logics, by passing in the arguments, but compiler throws error, so left it. (Sorry, if this is given in