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Verilog Case Statements

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18 Threads found on Verilog Case Statements
Hi, I'm running verilog-a for the first time and trying to get the following code to work: analog begin if (sIntegral > 0) integrand = V(bj); else integrand = 0; sIntegral = idt(integrand,.5); $fstrobe(fprt,"%f", integrand); $fstrobe(fprt,"%f", sIntegral); etc..... The behavior I want to see i
I?ve been trying to run a simulation for the following sample code. Requirement: Based on parameters generate a define which will be used further in the design. Observation : I can make this work if the defines are not used in the port definitions and only in the Behavioral code. module #( parameter PARAM_A
Hi there! I'm trying to make a FSM for the Fibonacci string, but I'm getting some warnings during the synthesis and I can't figure out why. This is the code : `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:02:45
In terms of the verilog LRM, a conditional or case statement can be used in place of a simple statement (See A.6.4 statements) This already answers your question.
I am confused I want to know what is difference between always and assign and where they use program 1st module and2gate (A,B,Y); input A,B; output Y; assign Y=A&B; endmodule program 2st module and2gate (A,B,Y); input A,B; output Y reg y always@(AorB); begin Y<=A&B; end endmodule
Yeah. I did follow the syntax. I m generating a set of 75 values in a module and i m trying to pass it to another module where the conditional assignments are needed. this is a piece of my code. always @(m1,kk01,kk02,kk03,kk11,kk12,kk13,kk21,kk22,kk23,kk31,kk32,kk33,kk41,kk42,kk43,kk51,kk52,kk53,kk61,kk62,kk63,kk71,kk72,kk73, kk81,kk82,kk83,kk
Hmmm, Google seems to produce a lot of useful results when you search for: "verilog fsm coding styles"
Hi, I need a help in writing a verilog code for some signals like CLK, CKE, and RESET with their delays. I have written the code according to my knowledge but there are some conflictions in that. Iam here attatching the related document along with my code please check it out and suggest me. thank
Dear all, As lots of books talk about inferring latches in hardware, when we miss few statements during coding like 1- not including else with if 2- not including default case with case statements.... but upon reading XST user manual examples I observed above are missings they not considered both of the above (...)
You can use case statements to generate packets in RTL verilog or VHDL. You can find many examples over the internet. A sample is here verilog case statement to generate packets in a Testbench.
Hello, I need to write a script which will transfer specific module/s in the verilog design from one place in the hierarchy into another. The problem occurs when I face design with ifdef and generate->case/if statements. I know this could be done, but this is a hard work, so I want to be sure that I won't reinvent the wheel. Maybe (...)
Hi, I am a verification guy and want to know if following verilog codes are valid or not: 1) always @( a & b) 2) always @(a || b) 3) always @(a && b) 4) always @(a | b) Thanks
Hi all, I want to write a configurable verilog code of case statement....please help me, if any idea... Example_1: In this simple example, i know how many case expressions may exist in my case loop...4: parameter COUNT_WIDTH = 4 case (COUNT_WIDTH) 4'b0001: something; 4'b0010: something; (...)
A 4-1 mux written in verilog case statement will be implemented in hardware as .....? A 4-1 mux written using if else statements in verilog will be implemented in hardware as ...? My question is both hardware implementation is same or different? pls explain elaborately......
anyone having any idea of doing /using sorting algorithm in verilog .... i have used it using comparators but it is taking big logic... kindly suggest any methods.. Thanks
In actual usage you may use an if condion without satisfiying all the possible combinations of the condition for example you want to implement if a=1 set output=1 otherwise output=0 possible verilog codes for this using if statement by a naive user if (a==1) begin
Can any body tell me which is better in Initial Statement in verilog Blocking or Non Blocking also in Task which is better.
Hi i had a question in verilog in an interview. ie.. if u r using nested if-else statements in your code and u find some timing problems. In that case how will u change your code (problem is with the nested if-else). Plz get me the solution.. haran