26 Threads found on edaboard.com: Verilog Code For Fir Filter
ASIC Design Methodologies and Tools (Digital) :: 09.03.2005 09:51 :: eda_wiz :: Replies: 6 :: Views: 15850
If u can get the book "Digital signal processing with field programmable gate arrays", I think there are a few examples of verilog code for fir filter design.
Digital Signal Processing :: 02.06.2008 15:22 :: soloktanjung :: Replies: 2 :: Views: 3449
hi can anyone send me the verilog code for fir filter
Digital Signal Processing :: 07.09.2010 14:12 :: ksmadhu111 :: Replies: 1 :: Views: 1366
can any one pls send me verilog code for fir low pass filter??
Digital Signal Processing :: 12.09.2012 10:14 :: sreenitha :: Replies: 0 :: Views: 411
I am trying to implement 8 tap (7th order) Low Pass fir filter in ASIC semi custom design by writing its verilog code & testbench .. How do I represent the filter coefficients in the code ( which may be +/- ve and have fractional parts) ..?
Can I write direct statements (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.04.2012 06:16 :: anishsingh :: Replies: 4 :: Views: 1004
Hi I am required to create a test bench to test my verilog code for fir filter of order 7 (low pass) design for cutoff 2 khz. While writing a testbench ho should I give in 8 bit binary inputs to test filter functionality ??
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.04.2012 02:45 :: anishsingh :: Replies: 2 :: Views: 491
Here is a way to test ur fir filter...
1. Get VHDL or verilog code for fir filter ready.
2. Generate data file for (sine+ noise) using C or any other scripting file.
This you can do in C simply as follows..
for (i=0; i< (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.09.2005 01:24 :: nand_gates :: Replies: 4 :: Views: 1918
Added after 1 minutes:
pls send matlab code and verilog code for image read and fir filter
EDA Jobs :: 04.10.2009 06:13 :: abithamol :: Replies: 0 :: Views: 2300
how can i generate a code for fir filter using software other than matlab.. i used matlab but the problem i faced was real variable data type was not supported by the software i use.. pls help me as early as possible.. how to generate a verilog or vhdl code using a software or a (...)
Digital Signal Processing :: 24.03.2013 14:34 :: jjsr :: Replies: 0 :: Views: 270
I think i have seen in the verilog code for DSP. You can pick up even this verilog code, do modify and filter out those unecessary module and do translation to VHDL by either Design Compiler or RTLCompiler.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.05.2008 04:28 :: atena :: Replies: 14 :: Views: 1400
first u have to do then u begining your new VLSI design is to search final solution of your problem in Xilinx and Altera sites :))
There are several verilog examples of fir on Xilinx site.
Digital Signal Processing :: 04.01.2006 06:50 :: GroundCtrl :: Replies: 7 :: Views: 2780
The RTL filter design is based on fixed number filter design, which can be realized by matlab and other tools, such as c/c++.
The main problem for the hardware implementation of the filter is the architecture and quantity noise. As we know, 1 bit can give 6dB SNR enhancement. So you must manage to get your system level (...)
ASIC Design Methodologies and Tools (Digital) :: 13.02.2006 00:10 :: zhustudio :: Replies: 2 :: Views: 2598
I am trying to write a verilog code for Decimation fir filter. Can any1 tell me how do we select the coefficients??
I did see a hardware structure where the Input is fed to a demux with select line as modulo counter and the output of the demux is connected to the rom each having even and (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.12.2008 23:00 :: haneet :: Replies: 1 :: Views: 848
I'm doing a project on altera quartus, where I need to implement a fir low pass filter in direct form. I was just about finishing writing it up, when I came to the realization that what I've done is not direct form (I don't think). My code is below, and I was wondering if anyone could suggest (...)
Digital Signal Processing :: 03.06.2011 18:38 :: jpglotzer :: Replies: 3 :: Views: 2530
I have tried a lot for syntesizing verilog code obtained using fdatool, pls anyone can tell me how we can syntesize the code in xilinx or altera
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.02.2012 06:09 :: blooz :: Replies: 3 :: Views: 454
my seminar uses an fir filter that has reduced number of multipliers. so my code need to consider the structure. do i need to code it in gate level?
the filter coeffficients obtained from matlab is 64 bit. how can i convert it to lower bits or how can i directly use them as signed numbers in (...)
Digital Signal Processing :: 23.01.2013 01:01 :: snehajose :: Replies: 1 :: Views: 248
i wrote fir filter and adaptive filter code in verilog i wanna test this code using matlap 7. i read articles from mathworks web. they said we can interface simulink and modelsim. if any one has already experience in this area. pls help me. i wanna know my code (...)
Digital Signal Processing :: 08.02.2005 19:01 :: aravind :: Replies: 1 :: Views: 1886
module fir_srg (clk, x, y); //----> Interface
// Tapped delay line array of bytes
reg tap0, tap1, tap2, tap3;
// for bit access use single vectors in verilog
always @(posedge clk) //----> Behavioral Style
begin : p1
// Compute output y
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.06.2005 07:42 :: superhet :: Replies: 2 :: Views: 956
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.06.2006 05:41 :: nczx :: Replies: 19 :: Views: 3292
I've never used Altera FPGAs, but I think that device has 54 18-bit MACs that can go 278 MHz. I don't know how easy/difficult it is to achieve maximum speed in Altera parts, but I would try using 6 MACs running at 220 MHz, with each one processing 11 filter taps.
In general, for good FPGA resource utilization, you should run the clock fast, use
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.10.2006 01:27 :: echo47 :: Replies: 14 :: Views: 1790
I need to implement fir filter for long tail of a pulse. I can do it with trational electronics filter but designing and implementing in verilog is a little confusing to see the starting point.
any good example or website which can guide me about design and implement process for (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.11.2006 09:07 :: Mirzaaur :: Replies: 2 :: Views: 868
can any one help me to develop code to convert a floating point number to binary and writing code in verilog.
can u sujjest some sites or material or can give any code for that
pls help. i have to develop a fir filter in verilog and in that i have a need (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.08.2007 05:31 :: rajsrikanth :: Replies: 4 :: Views: 3778
as I know , many analog design use C for delta_sigma modulator
and someone use matlab(simulink) design delta_sigma recently..
but it is idea case condition ..
and I know a tool called "smash " dolphin provide a mix mode simulation
maybe sometime we can use mix mode tool simulation whole chip
because deltaSigma AD need
1. frontend --> del
Professional Hardware and Electronics Design :: 18.06.2003 05:31 :: andy2000a :: Replies: 19 :: Views: 7929
This is code to implement fir by verilog for FPGA.
I have simulated it by Quartus 4.0 and find that the result is not corrected in the first cycle but corrected in the second cycle. I can not explain what reason ?
I attach my simulation file and mark the error for two cycles .
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.12.2004 03:05 :: hoangthanhtung :: Replies: 2 :: Views: 798
I have a problem.
I am into designing an array of bandpass filters so that it forms a filter bank.
I have designed the filter in matlab using fdatool and generated the hdl (verilog)
code from it.it's a 6'th order bpf with 3 biquads(IIR Butterworth).
pls do let me know that (...)
ASIC Design Methodologies and Tools (Digital) :: 11.10.2006 01:19 :: rsrinivas :: Replies: 2 :: Views: 969
How about a good book on digital logic design with verilog HDL, cause i used to code with verilog HDL?
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.09.2011 23:43 :: rockybc :: Replies: 3 :: Views: 414