15 Threads found on edaboard.com: Verilog Code For Fir Filter
How can I modify my fir filter to have an input and output that have a precision of 3 decimal places. I already constructed floating point computation but I dont know on how to link it with my filter in verilog. This is my code for fir filter: (...)
ASIC Design Methodologies and Tools (Digital) :: 04-14-2015 06:54 :: deepsetan :: Replies: 11 :: Views: 923
i am murali , i need an verilog code for 4 bit serial in parallel out shift register, 4 bit dual port distribted ram, 4 bit pipeline adder tree and 4 bit pipeline shift-add tree.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-05-2014 04:40 :: MURALIMAHARAJAN :: Replies: 1 :: Views: 1250
I am designing low power adpative filter in xilinx 14.6.But ,i am not getting correct code for that.
first for designing low power adaptive filter I should design low power or programmable fir filter.so,please help me.If you have (...)
Digital Signal Processing :: 07-18-2014 13:34 :: Pallavit :: Replies: 0 :: Views: 532
how can i generate a code for fir filter using software other than matlab.. i used matlab but the problem i faced was real variable data type was not supported by the software i use.. pls help me as early as possible.. how to generate a verilog or vhdl code using a software or a (...)
Digital Signal Processing :: 03-24-2013 18:34 :: jjsr :: Replies: 0 :: Views: 691
can any one pls send me verilog code for fir low pass filter??
Digital Signal Processing :: 09-12-2012 14:14 :: sreenitha :: Replies: 0 :: Views: 822
How do I represent a number such as -0.2 in binary in verilog code ????
Basically the same way that you do on pencil and paper, when required to use integer numbers only.
You need to define fractional number representations for signal and coefficients, according to the required signal dynamic and coefficient accuracy. A fraction
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-16-2012 09:00 :: FvM :: Replies: 4 :: Views: 1558
I have tried a lot for syntesizing verilog code obtained using fdatool, pls anyone can tell me how we can syntesize the code in xilinx or altera
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-11-2012 11:09 :: blooz :: Replies: 3 :: Views: 1039
I'm doing a project on altera quartus, where I need to implement a fir low pass filter in direct form. I was just about finishing writing it up, when I came to the realization that what I've done is not direct form (I don't think). My code is below, and I was wondering if anyone could suggest (...)
Digital Signal Processing :: 06-03-2011 22:38 :: jpglotzer :: Replies: 3 :: Views: 4054
hi can anyone send me the verilog code for fir filter
Digital Signal Processing :: 09-07-2010 18:12 :: ksmadhu111 :: Replies: 1 :: Views: 1994
Added after 1 minutes:
pls send matlab code and verilog code for image read and fir filter
EDA Jobs :: 10-04-2009 10:13 :: abithamol :: Replies: 0 :: Views: 3003
I am trying to write a verilog code for Decimation fir filter. Can any1 tell me how do we select the coefficients??
I did see a hardware structure where the Input is fed to a demux with select line as modulo counter and the output of the demux is connected to the rom each having even and (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-04-2008 04:00 :: haneet :: Replies: 1 :: Views: 1128
If u can get the book "Digital signal processing with field programmable gate arrays", I think there are a few examples of verilog code for fir filter design.
Digital Signal Processing :: 06-02-2008 19:22 :: soloktanjung :: Replies: 2 :: Views: 4146
Here is a way to test ur fir filter...
1. Get VHDL or verilog code for fir filter ready.
2. Generate data file for (sine+ noise) using C or any other scripting file.
This you can do in C simply as follows..
for (i=0; i< (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-07-2005 05:24 :: nand_gates :: Replies: 4 :: Views: 3271
4 tap filter eqn for ur design is:
y = (-1 * Tap0) + (3.75 * Tap1) + (3.75 * Tap2) + (-1 * Tap3)
while Rearranging it looks like:
y = +
- Tap3 +
Now Correlate this with ur verilog code:
y <= (tap
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-22-2005 12:22 :: Renjith :: Replies: 2 :: Views: 1335
ASIC Design Methodologies and Tools (Digital) :: 03-09-2005 14:51 :: eda_wiz :: Replies: 6 :: Views: 18092