15 Threads found on edaboard.com: Verilog Code For Matrix
Once again your treating verilog as software. A 2D array does not necessarily translate to a memory. Many times you will end up with a large array of FFs., which maybe is okay in this case as the entire array is single bits and only 240x128.
You really need to be aware you are designing a digital hardware design and what each line of code represen
ASIC Design Methodologies and Tools (Digital) :: 10-05-2016 09:32 :: ads-ee :: Replies: 2 :: Views: 199
I have a vector and a matrix of hexadecimal values stored in .mem files. I need to subtract this vector from each row of a matrix in each clock cycle.
I have read my files to my testbench file using $readmemh in verilog. How can I subtract them now?
I have used xilinx ip floating ip core for subtraction as well. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-11-2016 02:40 :: Mahnaz_m :: Replies: 0 :: Views: 12
I'm new to verrilog HDL...I want to write a program for matrix operations in verilog..please help me
Well first off don't think of verilog code as a progrm. verilog isn't a software language. Insstead think in terms of a schematic of a digital circuit, which you will then describe in (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-17-2015 02:40 :: ads-ee :: Replies: 4 :: Views: 697
mat<=((others=>(others=>'0')),(others=>(others=>'0')),(others=>(others=>'0'))); is to assign the elements in the matrix to 0 values in VHDL.
you can check the following links for verilog code as well as assigning the values into the
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-19-2015 07:54 :: TrickyDicky :: Replies: 6 :: Views: 767
for the most part System verilog is backwards compatible with verilog
ASIC Design Methodologies and Tools (Digital) :: 06-13-2014 13:50 :: rberek :: Replies: 5 :: Views: 986
Hi guys, i am new at verilog. I generated a working verilog file using Matlab HDL Generation Tool. I tested it with 16 binary bits using assign parameters and it worked for this values. But i need an input random binary matrix. The following code must use this matrix with 16 bits block. How (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-27-2013 06:34 :: kobay000 :: Replies: 0 :: Views: 525
Hi,I m new to FPGA.Can anyone pls guide.I want to implement a multiplier on FPGA. for that i will generate the bit stream in XILINX. But the code for interfacing any device for eg.keyboard,what to do with the code?How to implement,where to write,what are the steps after writing the code?? (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-01-2013 13:57 :: shaiko :: Replies: 5 :: Views: 2042
i want to write verilog code for 2 dimensional FFT which needs defining a 2 dimensional matrix and every element in this matrix is an array of 15 ...can anyone tell me how to write data in matrix..one way is defining an array of (no of rows* no of der any other method?
and also (...)
Elementary Electronic Questions :: 05-06-2012 11:33 :: jyt_19 :: Replies: 0 :: Views: 359
sir this is my project pls help me for writing code .and give some suggestion...
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-06-2012 12:42 :: harieandc :: Replies: 8 :: Views: 3036
you dont define where you're trying to implement this. FPGA, DSP, VHDL, verilog?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-21-2011 03:32 :: TrickyDicky :: Replies: 5 :: Views: 510
Can you tell me how to do same thing in verilog?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-12-2010 00:17 :: shitansh :: Replies: 9 :: Views: 3807
Appreciate if anyone has access to verilog/VHDL code for Gray Level Co-occurrence matrix (GLCM) for implementation on FPGA ORverilog/VHDL code for any general image processing operation that uses spatial convolution such as sobel / prewitt (...)
Digital Signal Processing :: 12-12-2009 03:45 :: my323 :: Replies: 0 :: Views: 2846
I'm working on matrix oriented Processor development (architecture, ISA).
I collected a lot of information about this kind of processing. I'm in architecture research and development stage.
I have some written code in verilog. This kind of processors are going to be used in science , video , multimedia, anywhere (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-14-2009 09:38 :: Bidza31 :: Replies: 0 :: Views: 778
Some months ago, I wrote a simple crude verilog module (sorry not VHDL) that displays "Hello World!" on the LCD of the Xilinx Spartan-3E Starter Kit. Maybe it will help you. Look in this long discussion for my message dated 07 June 2007:
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-03-2008 18:42 :: echo47 :: Replies: 3 :: Views: 4003
Hi every body,
I am looking for verilog code for matrix multiplication (not involving the use of a cordic core cause that would take alot of space on the FPGA.............I mean is it possible to have a code without CORDIC core used.........) .........if any one knows about it then (...)
ASIC Design Methodologies and Tools (Digital) :: 03-05-2003 14:24 :: Aircraft Maniac :: Replies: 0 :: Views: 5278