48 Threads found on edaboard.com: Verilog Dac
i want to generate 1MHz, 2MHz, 3MHz square wave in a parallel manner. and i want to increase or decrease the voltage and frequency for individual square how to design in verilog.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-09-2016 08:26 :: Bosechandran :: Replies: 4 :: Views: 349
I have a requirement to define an output with a more 'analog' feel then the straight forward digital definition that I currently have in place.
dac_out is defined as a digital output
This is simply 1 or 0 based on:
module dac (IOUTN, IOUTP, VDDA1V8,, BIAS, CLK, dac,
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-07-2015 07:01 :: DharmaSlice :: Replies: 0 :: Views: 580
hi I have completed my M.Tech in VLSI Design from C-dac, Mohali. I have knowledge about verilog, system verilog, OVM UVM methodologies, AHB\AXI protocols. Is there any opening of VLSI Engineer. Before this i have 2 year exp. in industrial automation(PLC,SCADA). Plz reply what should i do now
EDA Jobs :: 09-25-2013 12:16 :: pandit007 :: Replies: 0 :: Views: 636
Is there a way to simulate a digital to analog converter in ModelSim????? I have my verilog code that produces the 16 bit input to a dac . It would be really nice if I could somehow see the analog waveform in simulation...
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-08-2013 05:04 :: gnoble29 :: Replies: 2 :: Views: 1204
I've created a dac using veriloga(the code is below). My question is which function can I use in veriloga (in digital verilog the function posedge is used) to save the V(out) value only at the rising edge of the control signal?
Analog Circuit Design :: 03-05-2013 09:24 :: emont89 :: Replies: 0 :: Views: 542
I am no expert on this topic, but I can give it a try.
You can connect the output of your ADC to a ideal dac (verilog-A model or similar). You can then extract the simulation waveform of the dac output and calculate INL and DNL.
I personally prefer to write verilog-A models for both dac and an INL/DNL (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-21-2012 11:53 :: Yarrow :: Replies: 4 :: Views: 1793
My hspice 2008.10 can run normal simulations.
However, when get to verilogA models, it will complain something weird.
During .hdl command processing, loading verilog-A modules from
hsp-vacomp: Invoking the verilog-A compiler for (...)
Linux Software :: 02-09-2012 07:43 :: neoflash :: Replies: 0 :: Views: 1458
Can any one suggest verilog code for sawtooth wave form.?
thanks for spending time for read my question.
ASIC Design Methodologies and Tools (Digital) :: 07-14-2011 06:42 :: param426 :: Replies: 5 :: Views: 5080
In a delta sigma modulator, it is well-known that only dac and the first integrator can contribute to the output noise. It can also be tested by behavioral simulators such as Matlab and verilog-A.
I found that transient noise analysis is not match with noise analysis. An experienced designer told me that he
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-11-2011 04:58 :: Manjunatha_hv :: Replies: 9 :: Views: 4682
i having problem with my verilog dac..can anyone help me plsssssssss...
Digital Signal Processing :: 06-03-2011 11:48 :: asraf :: Replies: 0 :: Views: 990
verilog-A Sample Library - Analog/Digital Converters and Modulators
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-12-2011 14:25 :: pancho_hideboo :: Replies: 2 :: Views: 6449
I was wondering where I can find a tutorial that demonstrates the linking between verilog and verilog AMS in SMASH. Moreover, is there any pre-developed converter module ( ADC, dac) that I can use in SMASH? Even tutorials of Spice + verilog that use multi-bit ADCs and dacs would be very valuable. I already (...)
Analog Circuit Design :: 01-20-2011 16:26 :: GeniA :: Replies: 0 :: Views: 694
i have designed adc,dac and comparator in verilog-a. Now i have to simulate them by using hspice but i m not getting netlist for it.please help me out to get the netlist for this three modules...
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-29-2010 06:32 :: nil_rupali :: Replies: 0 :: Views: 1444
hay every one, i am new to verilog, tried to make some small programs like clock etc. now i want to design an ADC chip as one of my course projects. actually i want to design a chip that works as and ADC if the mode pin is high and dac if its low. plz gude me out, and suggest me that if its a nice project or not? and will a person having little ver
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-20-2010 19:23 :: princez :: Replies: 6 :: Views: 8530
SRAM design and layout??
Involves both VHDL/verilog and also designing some cells at transistor level.
you can do layout if u r interested.
ASIC Design Methodologies and Tools (Digital) :: 06-09-2010 22:33 :: somu.atluri :: Replies: 12 :: Views: 5820
Since it is not a very complex logic block, just do it by hand! It will simplify your design flow. You could use verilog-a to speed up the simulation but you will be adding only something like 80-100 gates to your design, so almost no speed impact...
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-04-2010 15:43 :: JoannesPaulus :: Replies: 2 :: Views: 1059
You can find the models you need.
Analog Circuit Design :: 03-28-2010 04:33 :: danda821 :: Replies: 1 :: Views: 2147
I'm new to FPGA and verilog. I have the Xilinx startes kit and I want to communicate from FPGA to dac section. dac needs SPI proto. to get initiated. Please let me know how to do that. I have user guide from xilinx and in that it has got good details about the protocol, timing dia. everything.Bu t I'm not able to implement in (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-04-2010 05:29 :: Prasanna hegde :: Replies: 2 :: Views: 1138
yes, it's possible.. I implemented a BPSK modulator in a spartan 3E fpga, only with verilog and schematics designs (that could be translated to verilog)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-24-2010 14:20 :: mersault :: Replies: 5 :: Views: 3139
You could also try to model things that are not critical to
bandwidth or accuracy, more simply. Like, the front end logic
probably could be verilog or veriloga. And of course for top
level type simulations the whole dac could be behavioral
Knowing when to fight, and when to fake it, is key.
Analog Circuit Design :: 02-10-2010 14:32 :: dick_freebird :: Replies: 3 :: Views: 1494
I am using ic5141 and wrote a simple verilog-ams code for 1-bit dac where input is digital signal and output is analog.After that i instantiated in schematic window for simulating it.
I reffered manuels to simulate this but i am not getting any proper idea for simulating mixed design.
For simulating any design, is it compulsory to go for "
Analog Circuit Design :: 12-25-2009 14:12 :: VINAY_RAO :: Replies: 0 :: Views: 951
How about use a 12-bit verilog-a counter, and use the output to drive the dac. increment the counter every cycle.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-12-2009 23:51 :: eecs4ever :: Replies: 18 :: Views: 2337
I've been learning the basics (very basic) of DSP and I wanted to try to implement things in verilog. Histograms dac->ADC etc. How does one go about doing this on an FPGA? I have the Spartan 3E starter kit. Not an FPGA built specifically for DSP, but should be enough to get something going.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-08-2009 16:34 :: laserbeak43 :: Replies: 0 :: Views: 730
anyone has tutorial on mixed-mode simulation? Maybe using a simple verilog as a test bench vector generator testing the dac? Thanks.
Analog Circuit Design :: 10-25-2009 06:32 :: ee171 :: Replies: 0 :: Views: 1393
I need to generate a sine wave from a LC tank based circuit and a Delta Sigma dac. The circuit seems quite simple (from an article of Roberts and Lu on BIST). All good except the resulting output is not a sinewave (close to it but not close enough) and since I am very new to verilog, I am quite sure the problem as to do with my c
Digital Signal Processing :: 06-26-2009 02:34 :: asalazar :: Replies: 0 :: Views: 1269
I have a project on pwm in verilog programming language. "pwm and one bit dac". The aim of this project is to convert the dıgıtal data to analog. Ihave found codes.
I am usıng xilinx spartan 3E kit
module PWM(clk, PWM_in, PWM_out);
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-25-2008 09:35 :: semesu :: Replies: 1 :: Views: 3171
I am looking for a synthesizer and a simulator for verilog with analog / verilog -AMS or something that would let me include analog parts in my design such as an op-amp / dac / ADC etc.
I searched google for such a tool for hours and did not find anything.
I would prefer a free tool... but tell me about it anyway even if it is (...)
Software Recommendations :: 10-04-2008 14:57 :: Lord Loh. :: Replies: 2 :: Views: 343
Dear jiangxb :
If I want to using verilog-A and transitor simulationusing spectre or Ultrasim.
Is it ok ? DO u knwo how to model the current cell using verilog-A , Thanks
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-12-2008 04:43 :: mitgrace :: Replies: 2 :: Views: 1535
Dear All :
I want to write current cell of verilog -A , Does anyone have the experiment ? Thanks
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-24-2008 03:04 :: mitgrace :: Replies: 3 :: Views: 700
hi all....I have designed a 10 bit 100 MHz current steering dac in Tanner EDA.... To measure SFDR i need to use an ideal ADC at the dac input.....But the problem is that Tanner doesnt support verilog A models for ideal ADC...and i cant find a spice netlist for an ideal 10 bit plz do help me....
Analog Circuit Design :: 05-09-2008 00:39 :: arjun_p_cet :: Replies: 0 :: Views: 819
I've just finished the SD modulator.Because of my poor verilog about filter,i want to find some tools which can provide ideal dac and simulate my .tran file by spectre directly.
Analog Circuit Design :: 04-29-2008 02:47 :: CISSE :: Replies: 0 :: Views: 711
I find modelwriter of cadence is very useful for verilog-a simulation.
I can produce lots of blocks of analog circuit automatically, such as adc, dac, ota, peak detector, VCO, PLL, and so on.
And the parameters of all blocks can be set as we like. And then use spectre to simulate.
It is quite useful. Recommend it to you.
And the detail of it
Analog Circuit Design :: 03-16-2008 12:20 :: gaom9 :: Replies: 2 :: Views: 1969
this is a verilog code for first-order DSM , maybe it is helpful!!
Analog Circuit Design :: 02-29-2008 02:10 :: sethtalk :: Replies: 1 :: Views: 1869
you means to implement a sigma-delta ADC, but can you tell me how this ADC receive analog input ?
and maybe verilog_AMS is anohter option.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-09-2007 07:42 :: ls000rhb :: Replies: 2 :: Views: 847
convert from verilog to VHDL
i really need help~~
module dac (dacout, dacin, Clk, Reset);
always @(SigmaLatch) (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-29-2007 03:21 :: kun :: Replies: 8 :: Views: 1088
I don't know how to convert verilog to VHDL, but the code you've shown won't work due to typographical errors.
The original module is in Xilinx application note 154, "Virtex Synthesizable Delta-Sigma dac":
Maybe someone else can help you convert it to VHDL.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-23-2007 12:19 :: echo47 :: Replies: 1 :: Views: 2226
i have read the allen's book about the i want to design the circuit and simulation for it.but i donnt know how to start.the software i know is cadence and matlab.and i know use the verilog-a to design the dac and the verilog to decimator and filter.But i am not sure.
Also,can anyone tell me the procedure in detail？
Analog Circuit Design :: 09-12-2007 07:57 :: Yanhui :: Replies: 18 :: Views: 3494
i need code vhdl code or verilog code for ADC ans dac please help me ..
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-07-2007 05:26 :: rajakash :: Replies: 3 :: Views: 4861
No, verilog and VHDL don't support analog.
Instead, you could use verilog-AMS or VHDL-AMS.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-04-2007 06:16 :: echo47 :: Replies: 4 :: Views: 2261
hello, I am test ing a audio project at Xinlinx FPGA, but now I am meeting a problem, anyboday know how to modify the ac97 chip lm4550's dac's sample rate, according to spec, I enable the register 2A, and also set the corresponding sample value at register 2C in my verilog code, but the sample rate seems has no change, I am confused at this problem
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-10-2007 15:14 :: maizic :: Replies: 0 :: Views: 722
I have implemented one with perl.The basic idea is simple and you can also implement with any language you are familiar with.
You can also use verilog-a module. refer to HSPICE (version newer than 2005.3) demo case in the HSPICE install directory.
Analog Circuit Design :: 07-24-2006 15:26 :: lovseed :: Replies: 3 :: Views: 1532
how to design a full digital sigma-delta modeulator for dac or fractional-N PLL ?can anyone provide some advices about full digital sigma-delta modulator ,are there some verilog coding for such a modulator in website?
Digital Signal Processing :: 07-20-2006 06:40 :: ls000rhb :: Replies: 1 :: Views: 1895
verilogA model can do that,
it is easy to write this va block, check veriloga reference.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-08-2006 08:42 :: swicap :: Replies: 6 :: Views: 2102
If you have Cadence EDA tools, the best starting point is to use verilog-A behav. model included in 'ahdlLib'. From there you can add extra features/non-idealities to that model and make your dac model more realistic.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-31-2006 19:26 :: willyboy19 :: Replies: 5 :: Views: 1541
Just anyone can tell me how to describe this digital integrator in 5th-order delta-sigma modulator with verilog /VHDL. A digital integrator need a register for a delay?then...5th-order delta-sigma modulator just need 5 integrators?then...a quantilizer just need a register? So we need 6 clocks pulse at least from IN to OUT ?
Digital Signal Processing :: 03-27-2006 03:45 :: feel_on_on :: Replies: 0 :: Views: 1602
ADC is mostly implemented with analog circuit(r-2r adc,flash adc)... so not possible to write verilog code
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-14-2006 10:47 :: eda_wiz :: Replies: 4 :: Views: 4913
I am using spartan 3 fpga board,I want to use its VGA port to display my output signals on the monitor,as far as i know you need a HDL code to program the port,if anyone can provide me verilog code,do i have to place it in my original verilog code which i have designed or download it seperately on the fpga
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-10-2005 17:52 :: fakeha_s :: Replies: 6 :: Views: 4429
You can actually design a macro model of an ideal dac to compare the inputs and the outputs. In some environments like Cadence, you can write verilog A models
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-11-2005 15:58 :: Vamsi Mocherla :: Replies: 3 :: Views: 1269