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48 Threads found on edaboard.com: Verilog Dac
Dear all, i want to generate 1MHz, 2MHz, 3MHz square wave in a parallel manner. and i want to increase or decrease the voltage and frequency for individual square how to design in verilog. hi, you can produce n number of square waves using your clock..for that, what is your clock frequency and you can
Hi, I have a requirement to define an output with a more 'analog' feel then the straight forward digital definition that I currently have in place. dac_out is defined as a digital output This is simply 1 or 0 based on: ------ module dac (IOUTN, IOUTP, VDDA1V8,, BIAS, CLK, dac, ); inout (...)
hi I have completed my M.Tech in VLSI Design from C-dac, Mohali. I have knowledge about verilog, system verilog, OVM UVM methodologies, AHB\AXI protocols. Is there any opening of VLSI Engineer. Before this i have 2 year exp. in industrial automation(PLC,SCADA). Plz reply what should i do now
Is there a way to simulate a digital to analog converter in ModelSim????? I have my verilog code that produces the 16 bit input to a dac . It would be really nice if I could somehow see the analog waveform in simulation...
I've created a dac using veriloga(the code is below). My question is which function can I use in veriloga (in digital verilog the function posedge is used) to save the V(out) value only at the rising edge of the control signal? module dac_verilog(ctrl,b0,b1,b2,b3,b4,out); input (...)
I am no expert on this topic, but I can give it a try. You can connect the output of your ADC to a ideal dac (verilog-A model or similar). You can then extract the simulation waveform of the dac output and calculate INL and DNL. I personally prefer to write verilog-A models for both dac and an INL/DNL (...)
My hspice 2008.10 can run normal simulations. However, when get to verilogA models, it will complain something weird. During .hdl command processing, loading verilog-A modules from './dac.va'. hsp-vacomp: hsp-vacomp: Invoking the verilog-A compiler for (...)
The question isn't clear. verilog can't describe analog waveforms, it can at best generate a numerical variable that represents a waveform and may be output by a dac. A sawtooth waveform would be simply represented by a counter that's continuously incremented with overflow.
Hello naderi, In a delta sigma modulator, it is well-known that only dac and the first integrator can contribute to the output noise. It can also be tested by behavioral simulators such as Matlab and verilog-A. I found that transient noise analysis is not match with noise analysis. An experienced designer told me that he
i having problem with my verilog dac..can anyone help me plsssssssss... module dac5(clk,reset,dac_mosi,dac_sck,dac_cs,spi_ss_b,amp_cs,ad_conv,sf_ce0,fpga_init_b); input clk; input reset; output dac_mosi; output dac_sck; output (...)
verilog-A Sample Library - Analog/Digital Converters and Modulators
I was wondering where I can find a tutorial that demonstrates the linking between verilog and verilog AMS in SMASH. Moreover, is there any pre-developed converter module ( ADC, dac) that I can use in SMASH? Even tutorials of Spice + verilog that use multi-bit ADCs and dacs would be very valuable. I already (...)
i have designed adc,dac and comparator in verilog-a. Now i have to simulate them by using hspice but i m not getting netlist for it.please help me out to get the netlist for this three modules...
hay every one, i am new to verilog, tried to make some small programs like clock etc. now i want to design an ADC chip as one of my course projects. actually i want to design a chip that works as and ADC if the mode pin is high and dac if its low. plz gude me out, and suggest me that if its a nice project or not? and will a person having little ver
SRAM design and layout?? Involves both VHDL/verilog and also designing some cells at transistor level. you can do layout if u r interested.
Since it is not a very complex logic block, just do it by hand! It will simplify your design flow. You could use verilog-a to speed up the simulation but you will be adding only something like 80-100 gates to your design, so almost no speed impact...
check here You can find the models you need.
Hi all, I'm new to FPGA and verilog. I have the Xilinx startes kit and I want to communicate from FPGA to dac section. dac needs SPI proto. to get initiated. Please let me know how to do that. I have user guide from xilinx and in that it has got good details about the protocol, timing dia. everything.Bu t I'm not able to implement in (...)
yes, it's possible.. I implemented a BPSK modulator in a spartan 3E fpga, only with verilog and schematics designs (that could be translated to verilog)
You could also try to model things that are not critical to bandwidth or accuracy, more simply. Like, the front end logic probably could be verilog or veriloga. And of course for top level type simulations the whole dac could be behavioral most likely. Knowing when to fight, and when to fake it, is key.
hi,, I am using ic5141 and wrote a simple verilog-ams code for 1-bit dac where input is digital signal and output is analog.After that i instantiated in schematic window for simulating it. I reffered manuels to simulate this but i am not getting any proper idea for simulating mixed design. For simulating any design, is it compulsory to go for "
Hm... How about use a 12-bit verilog-a counter, and use the output to drive the dac. increment the counter every cycle.
Hi, I've been learning the basics (very basic) of DSP and I wanted to try to implement things in verilog. Histograms dac->ADC etc. How does one go about doing this on an FPGA? I have the Spartan 3E starter kit. Not an FPGA built specifically for DSP, but should be enough to get something going.
Hi guys, anyone has tutorial on mixed-mode simulation? Maybe using a simple verilog as a test bench vector generator testing the dac? Thanks.
Hi everyone, I need to generate a sine wave from a LC tank based circuit and a Delta Sigma dac. The circuit seems quite simple (from an article of Roberts and Lu on BIST). All good except the resulting output is not a sinewave (close to it but not close enough) and since I am very new to verilog, I am quite sure the problem as to do with my c
Hi, I have a project on pwm in verilog programming language. "pwm and one bit dac". The aim of this project is to convert the dıgıtal data to analog. Ihave found codes. I am usıng xilinx spartan 3E kit module PWM(clk, PWM_in, PWM_out); input clk; input PWM_in; output PWM_out; reg PWM_accumulator; alway
Hi... I am looking for a synthesizer and a simulator for verilog with analog / verilog -AMS or something that would let me include analog parts in my design such as an op-amp / dac / ADC etc. I searched google for such a tool for hours and did not find anything. I would prefer a free tool... but tell me about it anyway even if it is (...)
Dear jiangxb : If I want to using verilog-A and transitor simulationusing spectre or Ultrasim. Is it ok ? DO u knwo how to model the current cell using verilog-A , Thanks
Dear All : I want to write current cell of verilog -A , Does anyone have the experiment ? Thanks
hi all....I have designed a 10 bit 100 MHz current steering dac in Tanner EDA.... To measure SFDR i need to use an ideal ADC at the dac input.....But the problem is that Tanner doesnt support verilog A models for ideal ADC...and i cant find a spice netlist for an ideal 10 bit plz do help me....
I've just finished the SD modulator.Because of my poor verilog about filter,i want to find some tools which can provide ideal dac and simulate my .tran file by spectre directly.
I find modelwriter of cadence is very useful for verilog-a simulation. I can produce lots of blocks of analog circuit automatically, such as adc, dac, ota, peak detector, VCO, PLL, and so on. And the parameters of all blocks can be set as we like. And then use spectre to simulate. It is quite useful. Recommend it to you. And the detail of it
this is a verilog code for first-order DSM , maybe it is helpful!!
you means to implement a sigma-delta ADC, but can you tell me how this ADC receive analog input ? and maybe verilog_AMS is anohter option. BR. ls000rhb
convert from verilog to VHDL i really need help~~ module dac (dacout, dacin, Clk, Reset); output dacout; reg dacout; input dacin; input Clk; input Reset; reg DeltaAdder; reg SigmaAdder; reg SigmaLatch; reg DeltaB; always @(SigmaLatch) (...)
I don't know how to convert verilog to VHDL, but the code you've shown won't work due to typographical errors. The original module is in Xilinx application note 154, "Virtex Synthesizable Delta-Sigma dac": Maybe someone else can help you convert it to VHDL.
i have read the allen's book about the i want to design the circuit and simulation for it.but i donnt know how to start.the software i know is cadence and matlab.and i know use the verilog-a to design the dac and the verilog to decimator and filter.But i am not sure. Also,can anyone tell me the procedure in detail? [
hi friends,, i need code vhdl code or verilog code for ADC ans dac please help me .. with thanks raj..
No, verilog and VHDL don't support analog. Instead, you could use verilog-AMS or VHDL-AMS.
hello, I am test ing a audio project at Xinlinx FPGA, but now I am meeting a problem, anyboday know how to modify the ac97 chip lm4550's dac's sample rate, according to spec, I enable the register 2A, and also set the corresponding sample value at register 2C in my verilog code, but the sample rate seems has no change, I am confused at this problem
I have implemented one with perl.The basic idea is simple and you can also implement with any language you are familiar with. You can also use verilog-a module. refer to HSPICE (version newer than 2005.3) demo case in the HSPICE install directory.
how to design a full digital sigma-delta modeulator for dac or fractional-N PLL ?can anyone provide some advices about full digital sigma-delta modulator ,are there some verilog coding for such a modulator in website?
hello all, i am designing an ADC, and i was told that there is a way to create a verilog model for a block which can be connected to the ADC digital outputs. the verilog block can then write the digital codes from the ADC to a file. how can i do this many thanks
If you have Cadence EDA tools, the best starting point is to use verilog-A behav. model included in 'ahdlLib'. From there you can add extra features/non-idealities to that model and make your dac model more realistic.
hi,all Just anyone can tell me how to describe this digital integrator in 5th-order delta-sigma modulator with verilog /VHDL. A digital integrator need a register for a delay?then...5th-order delta-sigma modulator just need 5 integrators?then...a quantilizer just need a register? So we need 6 clocks pulse at least from IN to OUT ? this
ADC is mostly implemented with analog circuit(r-2r adc,flash adc)... so not possible to write verilog code
I am using spartan 3 fpga board,I want to use its VGA port to display my output signals on the monitor,as far as i know you need a HDL code to program the port,if anyone can provide me verilog code,do i have to place it in my original verilog code which i have designed or download it seperately on the fpga Thanks
You can actually design a macro model of an ideal dac to compare the inputs and the outputs. In some environments like Cadence, you can write verilog A models