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## Verilog Floating |

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88 Threads found on edaboard.com: **Verilog Floating**

Hi, I need a c code for testing the full functionality of my Risc-based microcontroller designed through **verilog** HDL. Apparently i need to write a c code which totally occupies the RAM and uses whole general Instruction Sets of PIC16f8X mirocontrollers. I wonder if ANYONE could help me out.

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-12-2016 11:56 :: ahmad.sb101 :: Replies: **1** :: Views: **488**

Unless you reading decimal number strings in your **verilog** code, there won't be a decimal number format used. Please reconsider.
Number formats with decimal point used in digital processing are **floating** point or fixed point. Possibly constants are specified as decimal numbers in your code.

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-14-2016 11:43 :: FvM :: Replies: **5** :: Views: **573**

Not a real LVS.
Few of the Ports might be **floating** (based on your **verilog**)
But to confirm this, Run LVS with Calibre (or any sign off) tool

ASIC Design Methodologies and Tools (Digital) :: 08-31-2016 13:50 :: Prashanthanilm :: Replies: **3** :: Views: **776**

Hi,
I have a vector and a matrix of hexadecimal values stored in .mem files. I need to subtract this vector from each row of a matrix in each clock cycle.
I have read my files to my testbench file using $readmemh in **verilog**. How can I subtract them now?
I have used xilinx ip **floating** ip core for subtraction as well.
Here is my code but this c

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-11-2016 06:40 :: Mahnaz_m :: Replies: **0** :: Views: **12**

Hi,
I am designing a hybrid content addressable memory (CAM) using cadence and I need to build a **verilog**-A block to switch modes. In the read mode, I need to pre-charge some nodes then make them **floating**. I tried different **verilog**-a lines but the code always fails. For example, I tried using the following line that I found while (...)

ASIC Design Methodologies and Tools (Digital) :: 06-03-2015 20:21 :: Engineer4ever :: Replies: **0** :: Views: **633**

If you want b to have the value 'b1111, then just do b = n;
$realtobits returns the simulator's internal representation of a real/**floating** number. It's only purpose in **verilog** was that was the only way to pass a real value through module port. You would then use the $bitsto

ASIC Design Methodologies and Tools (Digital) :: 04-29-2015 15:26 :: dave_59 :: Replies: **3** :: Views: **3613**

Hi guys,
How can I modify my FIR filter to have an input and output that have a precision of 3 decimal places. I already constructed **floating** point computation but I dont know on how to link it with my filter in **verilog**. This is my code for FIR filter:
module FIR_filter
#(parameter STAGES = 4)
(
input CLK,
input RST,

ASIC Design Methodologies and Tools (Digital) :: 04-14-2015 06:54 :: deepsetan :: Replies: **11** :: Views: **1168**

i have to design an adder module in **verilog**; input values are 0.1519 and -1.02123
You don't want **floating** point arithmetic you want to implement fixed point arithmetic.
The whole point of using **floating** point is to be able to represent numbers like 0.0000000000000000234 and 234000000000000000 in a small number

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-02-2015 15:48 :: ads-ee :: Replies: **8** :: Views: **1715**

hi,
I am trying to write a code which will recieve real values from the real time enviroment.but **verilog** does not support real value synthesis, so how will i write a code in such situation,i don't want a truncated form of the real number suppose 2.3145 >2(this i don't want).
so how do i process real value in the codeE?

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-17-2015 23:10 :: Indrajit Ghosh :: Replies: **1** :: Views: **564**

Unfortunate the **floating** point vendor libraries aren't provided as VHDL sources, most likely they even haven't been written in VHDL or **verilog**. They are designed to use the DSP hardware of different FPGA families in an optimal way, using respective low-level primitives. Altera e.g. is typically writing this stuff in AHDL.
For the same reason, wr

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-09-2015 11:39 :: FvM :: Replies: **7** :: Views: **1134**

I would also add CORDIC algorithm and look-up table (optionally with linear interpolation) to the candidate list.
Of course it doesn't matter if you are using **verilog** or a different hardware description method.

ASIC Design Methodologies and Tools (Digital) :: 02-07-2015 12:34 :: FvM :: Replies: **3** :: Views: **875**

Hi.
I want to know how to handle of **floating** point in **verilog**.
for example, 12.341 × 73.928
How do you usually handle of **floating** point in **verilog**?
In my case, I just take 10000 times to each them.
but this problem is not accurate.
so I need your usually methods.

ASIC Design Methodologies and Tools (Digital) :: 01-27-2015 02:43 :: u24c02 :: Replies: **1** :: Views: **896**

I am trying to implement a **floating** point multiplier on spartan3E using **verilog**. And I want to display the result in LCD(spartan3E 16x2 LCD).
How can we convert **floating** point to integer format in **verilog**?
How can we display the **floating** point number in LCD?
And also I wand to give input to the (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-09-2014 13:30 :: ads-ee :: Replies: **4** :: Views: **1924**

I'm trying to implement a linear programming problem on FPGA. I have used real data type to generate **floating** point numbers. The program compiled fine, but when I'm trying to synthesize it for my Xilinx Spartan-3E FPGA board it shows error that real is not supported by **verilog**. It seems that we cannot use real for synthesizable codes. So any sugges

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-31-2014 15:12 :: akipro :: Replies: **2** :: Views: **964**

Hi,
I am trying to do a code for do division using **verilog** that is work with fpga. The thing is division operator is not syntyhesizable.I am using fixed point arithmetic to represent a number (includes fraction),think the only methode to do it is loop baised substraction methode or quotient remainder methodeIis there any other possibility
?

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-30-2014 11:44 :: dipin :: Replies: **20** :: Views: **5738**

Hi,
I need to implement **floating** point arithmetic in **verilog**. I am aware of the fact that **verilog** does not support **floating** numbers.
Any hints on implementation of **floating** point arithmetic in **verilog** would be appreciated.
Thanks!

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-27-2014 19:05 :: supi :: Replies: **0** :: Views: **639**

Hi,
after running RTL Compiler I get a **verilog** netlist without vdd! and vss! ports. I think the reason is the .lib library that does not provide them for the standard cells. (but they are declared in .lef). Im not sure if this is a problem or not...
When running Encounter after init_design I do the following:
(Power pins are initialized by "se

ASIC Design Methodologies and Tools (Digital) :: 09-24-2013 12:42 :: party-pansen :: Replies: **2** :: Views: **3791**

hi,
I am trying to generate IEEE 754 **floating** point IFFT using Xilinx ipcores and **verilog**, but it is giving fft of the patterns as the answer, I tried by putting fft_inv=0 varying fwd_inv_we ='1' and then fwd_inv_we ='0' but i didnot get the proper answer. do anybody can help me solving the problem
..?

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-17-2013 03:34 :: Renjith Kumar :: Replies: **0** :: Views: **764**

Assuming the file in like :
.1
.12
.15
.2
.26
.3
and so on
write code like this
integer in,i,out;
real data;
initial begin
in = $fopen("input.txt,"rb");
out = $fopen("output","w");
if(!in) $display("File Open Error!");
if(!out) $display("File Open Error!");
i = $fscanf(in,"%f",data);
i

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-23-2013 15:56 :: sherif123 :: Replies: **2** :: Views: **1699**

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-18-2013 19:15 :: ads_ee :: Replies: **3** :: Views: **1291**

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-08-2013 05:14 :: apolama :: Replies: **1** :: Views: **3037**

I think Xilinx used to have a **verilog**->VHDL converter. check their website.

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-26-2012 21:02 :: barry :: Replies: **8** :: Views: **831**

Hi,
I want to write **verilog** code for **floating** point to integer conversion... Can anybody help me have any materials?
If u have can u pls send to me?......

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-03-2012 07:55 :: raaja :: Replies: **0** :: Views: **1001**

Hi,
I have a project on writing a n*n matrix inversion by using **verilog** code. I hope can doing this by using QR decomposition. Can anyone give me some clue on:
1) how can making the code is suitable for n*n matrix by just changing the parameter ?
2) a module that can do **floating** point division.

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-30-2012 14:23 :: sffong2 :: Replies: **2** :: Views: **2689**

Hi,
You have to consider using fixed point implementation (or **floating** point implementation) to handle the decimal number with points in your initial **verilog** code to make it synthesizable by the synthesis tool (such as ISE). Consider this tutorial:

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-21-2012 17:56 :: soloktanjung :: Replies: **2** :: Views: **654**

Hello Sir/Madam,
I have Spartan6 FPGA SP605 Evaluation kit. Using IP core generator, I wrote the program of **floating** point addition/subtraction program and I downloaded into the kit. But I have problem regarding to display result. So, plz suggest me a solution for that.
One more doubt, How can we give the input value to HDL program??

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-15-2012 11:46 :: vishal011990 :: Replies: **1** :: Views: **1286**

I need help with conversion from **floating** point decimal to binary and viceversa using **verilog** HDL, on Xilinx or Altera platform.
I want some suggestions regarding methods or algorithms that could help me with the conversions.
Thanks.

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-21-2012 14:03 :: ranj1011 :: Replies: **3** :: Views: **1075**

I am doing mini project on **floating** point arithmetic unit.
So please post code written either in VHDL or **verilog** otherwise give some links related to this...

PC Programming and Interfacing :: 03-03-2012 14:38 :: Arunkumar Wali :: Replies: **1** :: Views: **1173**

hi...i currently working mu final project that would need me to use this conversion. Here what i'm trying to do:
1. let say i have this number in decimal 6.23456. I want to multiply this value with other value (integer) and display the result ( in fraction num) on seven segment using **verilog** code.
for example:
value a=

Digital communication :: 12-02-2011 17:25 :: blooz :: Replies: **2** :: Views: **1705**

A.o.a:
In **verilog** HDL programming,I got some **floating** point arithmetic's to perform.I need to multiply a **floating** point number but problem is I am confused how to write **verilog** code that reads number convert it to fixed Q n.m format ....I know all the basics of Q n.m but problem is the algorithm behind this (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-14-2011 13:36 :: vickyuet :: Replies: **1** :: Views: **2591**

Why are you using a **verilog** testbench with a VHDL entity? wouldnt it be easier to stick to one language?

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-31-2011 07:13 :: TrickyDicky :: Replies: **2** :: Views: **969**

Hello,
I need to
1. convert integer to fixed point
2. Then perform functions such as division and exponential equation
Do you know any library or function for this? I know about mega functions but that is for **floating** point and it will require alot of resources that will be needed for other computations in my system
Thank you,

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-20-2011 15:09 :: chikaofili :: Replies: **0** :: Views: **1465**

Hello,
I know there is the $realtobits and $bitstoreal. But that is for double precision.
I need help in converting from integer to **floating** point (single precision). Are there libraries for that in **verilog**?
Thanks in advance
Chika

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-20-2011 01:00 :: chikaofili :: Replies: **1** :: Views: **3401**

Hello,
I am working with an equation Y= 1-exp(-a/b)
a and b are inputs (integers) from a different module in my **verilog** code.
Y is output
a/b ranges from
I working on a exponential algorithm that requires **floating** point as an input
My question is, how do I convert 'a/b' to a **floating** point representation . So I can use that

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-19-2011 22:11 :: chikaofili :: Replies: **0** :: Views: **768**

Hello,
What is the best way to read a textfile that contains decimal number (eg. 2.987) into **verilog**?
At the moment, I convert the values to hex using matlab (using num2hex). But when I use readmemh, it assumes that the 32bit variable is a 'regular' number and not a **floating** number?
Any suggestion will be greatly appreciated.
Thanks!

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-11-2011 22:22 :: chikaofili :: Replies: **0** :: Views: **2680**

Dear all
I am implementing a algorithm of kurtosis in FPGA.
I need 64 bit division in that.
Can anyone help me in this regards
---------- Post added at 04:59 ---------- Previous post was at 04:58 ----------
in FPGA means in **verilog**.
sorry for that

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-02-2011 03:59 :: shahbaz.ele :: Replies: **2** :: Views: **979**

Most design compilers support mixed mode, VHDL components can be instantiated as modules in the **verilog** code.

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-26-2011 12:33 :: FvM :: Replies: **4** :: Views: **809**

but...i need the step...how to divide the ieee754 binary **floating** point....because i need to write it in **verilog**.....

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-25-2011 12:12 :: watabe112 :: Replies: **3** :: Views: **753**

can anyone help me how to coding for this 2 step....using **verilog**.......please help

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-11-2011 14:49 :: watabe112 :: Replies: **0** :: Views: **1852**

HI,
I am Masters Student. for my project purpose i need some **floating** point calculation. but the input is in 16bit fixed point value. I need to convert this 16bit fixed value to IEEE64 bit **floating** format.
7380H = 0111 0011 1000 0000
convert into
0 (100 0000 1101) (1100 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000)
can any

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-31-2010 12:08 :: marufsust :: Replies: **4** :: Views: **5864**

Hello All!
Is anybody aware of where can I find the "University of Guelph **floating**-Point Arithmetic" library - "uog_fp_arith"? Is it free or not? How can I use it?
Google seems to be not very friendly regarding this information.
Besides, I am interested in any HDL package (preferably in **verilog**) that involves IEEE 32 bit single precision fl

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-11-2010 07:21 :: uglyduck :: Replies: **1** :: Views: **960**

e_xk1={1/8};
and
e_xk2={-1/8};
1) what are the resulting values in binary in e_xk1 and e_xk2??
2) how are they calculated?
3) what should be the correct declarations for e_xk1 and e_xk2?

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-06-2010 19:10 :: jameela :: Replies: **4** :: Views: **4439**

Hi,
How can we design a divider so that the we can preseve the value after decimal point in **verilog** HDL
Ex: If we need to divide the 3'b100 by 2 we will do it by right shifting 3'b100 by 1 time.
if we need to divide 3'b100 by 8 we will do it by right shifting 3'b100 by 3 times. But we cant preserve the value after the decimal pont ie., 0.1 in

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-05-2010 06:45 :: muni123 :: Replies: **1** :: Views: **980**

The first step is to implement the **floating** point unit. Then, you use the butterfly structure to make the FFT.
For to start in **floating** point unit:
and FFT

Digital Signal Processing :: 01-03-2010 12:30 :: jody :: Replies: **2** :: Views: **5109**

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-11-2009 11:10 :: priyanani :: Replies: **0** :: Views: **688**

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-15-2009 05:15 :: priyanani :: Replies: **0** :: Views: **3639**

i am doing my project in **verilog**..there i want to do calculation using **floating** point kindly anyone reply me how to represent **floating** point numbers in **verilog**....i will be very thankful..

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-09-2009 04:59 :: pinkyvidya :: Replies: **2** :: Views: **4664**

I have a confusion involves the SNR comparison of DSM simulated in MATLAB and VA. In MATLAB, I can get the theoretical maximum SNR (88dB) using transfer function blocks and quantizer block. But in VA, it gave me 68dB (I used the laplace transfer function in VA to create my loop filters, and quantizers and DAC are 16 levels). I don't understand why

Analog Circuit Design :: 04-02-2008 07:36 :: jowong1 :: Replies: **6** :: Views: **3880**

Hai all,
What are the various checks that are to be perfomed on prelayout **verilog** netlist by physical design engineer , before implementing P& R .
Regards,
KVB

ASIC Design Methodologies and Tools (Digital) :: 03-17-2009 06:51 :: viswanadh_babu :: Replies: **1** :: Views: **1371**

Hi all
i want to implement the following mathematical equation in **verilog**:
slopeup=(y2-y1)/(x2-x1)
slopeup after calculations will be like 0.01456... or -0.013478......... etc.
Plz can anybody tell me how to accomodate numbers like this in **verilog**???? Plz reply soon. Waiting

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-19-2008 06:42 :: saima_a :: Replies: **8** :: Views: **1631**

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