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114 Threads found on Verilog Signed
Hi , In VHDL we have a function to convert std_logic_vector to signed data we have anything like that in verilog to convert in to signed type in verilog. for example i have wire diff; I want to convert it into absolute value. Thanks Alka
Declare your signals as signed, like so: input signed X; input signed h_0; input signed h_1; // etc
What compiler you use? Using verilog 2001 compatibility?
twocmplement and mul_unsigned don't exist in the verilog language. Why don't you simply let the compiler do the hard work for you? (assumes verilog 2001) reg signed a=123, b=-77; wire signed y = a * b; Gives result -9471
how to represent negative numbers without using two's compliment method in verilog? Obscure sneaky solution: use a real number! The IEEE 754 floating point format contains a sign bit, a positive exponent field (with implied bias), and a positive fraction field. It has no two's compliment parts.
Dear Sir, This example describes an 8-bit signed multiplier with registered I/O in verilog HDL. Synthesis tools detect multiplier designs in HDL code and infer lpm_mult megafunction. I hope it is useful for you. Best Regards
I need some solutions for signed floating point number processing by using VHDL or verilog like add, sub, and multiply. Is there anybody who can help me. Thank in advance
What software tools and language are you using? When compiling VHDL or verilog with XST, you can simply use the "*" multiply operator and signed operands. Refer to the "Arithmetic Operations" section in the XST User Guide. XST will automatically infer the multiplier. This makes your HDL easier to read and more portable than explicitly instantiat
He's asking about the Xilinx FPGA block that multiplies two signed (two's compliment) 18-bit integers giving a signed 36-bit product. Here's a verilog example that I created for a question regarding Spartan 3 multiplier speed:
Hi all, I am new to verilog and want to build a 2's Complement Shifter. I found %displayb(8'b0001_1000>>2); //Output 0000_0110 %displayb(8'b1001_1000>>2); //Output 0010_0110 So, ">>" is unsigned shift. How can I build a signed (2's Complement) shift based on >>? i.e. I want 8'b1001_1000>>2 //Output 1110_0110 Any suggestions (...)
im doing a project in which i need to add two signed numbers. how can i check for underflow and overflow? module stimulus; reg signed a,b; wire signed c; signed_adder my_adder(a,b,c); initial begin $monitor($time, " a = %d, b = %d, c = %d", a, b, c); end initial begin a = 127; b = 127; end (...)
Hi, I am wondering, how does a 8-bit signed adder work. there are 3 inputs a, b, cin and 2 outputs sum, cout normally for unsigned operation, the msb is sent to cout, but for signed operation, should the msb be sent to cout? how do we know which is carry bit? how do we propagate the sign (+ or -) to the next (...)
Hi all, I heard that verilog has integer type. Someone said integer can be signed or unsigned. How to declare signed integer? And what's the difference with integer and reg signed (2's complement) ? Any suggestions will be appreciated! Best regards, Davy
Hi, In fixed-point multiplication, we should add an extended sign bit in the multiplication process . Example below: 1.110 -0.25 B X 0.110 0.75 C ------------------------- 0000 111110 11110 0000 ----------------------------- 11110100 -0.1875 A I have try to do a ve
Hi, I am currently doing a FFT for 8 point. Basically, I have problem in fixed-point multiplication because there is a extended sign bit before the adding. I have no idea on how to write this in verilog code. I try with this verilog code : assign A = B*C but it giving a wrong answer. the example of calculation is shown below:
Hi, I am currently doing multiplication with 2 different value of Q which is from ROM. Below is an example of code of top module : top (....) .. .. assign tmpMult_1 = $signed(A) * $signed(Q); // Q=0.7071 assign tmpMult2_1 = tmpMult_1 - ($signed(B) * $signed(Q)); // Q= -0.7071 .. .. endmodule I (...)
while using the fwrite in verilog....... as mentioned below.... $fwrite(file,"a=%d @=%d",a,addr); if the value of a is negative i am getting the data in the file as.........for eg....-1 as 65535 but i need to print it as -1 in the file do any one know other format of writting the data so i colud write negative values as
when i refered to verilog book, i can generate only signed random no. is there any possibilty to generate unsigned random no in verilog.
hi can anyone upload a software for implementing verilog code...
Hi all, I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys. And confused with the example below, why split unsigned and signed + and *? //=====Unintended behavior====== input signed a; input signed b; output z; // product width is 8 bits (not 12!) assign z = (...)
I would like to design a first order IIR high filter with equeation y = x - x + a * y I wrote the following verilog code, but the result is not correct . Can any one tell me why? input wire signed Xn, output reg signed Yn, parameter a = 0.9; reg signed Xn-1; wire signed diff = Xn-Xn-1; a
Hi, In my opinion, I would say task n function is something like "assign" and "always" in verilog. Why? For example, we can model combinational circuit using both statement (assign or always). But why we still need assign then. I think it is still the same reason why we still have "function". As for me, the rule of thumb is I always u
Hi... I have been trying to a verilog code for 8 bit signed adder... To add the negative number we complement it and add it with the positive number with a carry in as '1'. However when we get the carry out of the above process as zeros then we have to compute the two's complement of the result. For this we have to complement the result and a
hi all, is it possible to use the "+" in verilog language and expect the compiler to make the logic for an adder. e.g input a; input b; output c; assign c = a + b; is code like this synthesizable or would i actually have to look at making an adder from logic gates etc. thanks
I have a question regarding verilog integer data types. The default integer size is 32 bit in verilog. Can we extend it? In VHDL we can have something like, Max_Time : in integer range 0 to 255; How do we express this in verilog? Thanks Swapnil
Is there any way that i can found out the minimum of N-Numbers with minimum effort using verilog or VHDL
Hi, I have a brief question relating to some verilog for a sinc3 decimation filter. In the code, I believe 2s complement is being used for the accumulation process, however, I cant quite understand what is going on. As I do not have a verilog simulator at the moment, I am hoping someone could explain it to me. The relative parts of the code
hi.......... i need a verilog code 4 ....... 4 a 16 multiplier of signed numbers by implementing the technique of correction vector(use only one 16bit carry look ahead adder) plz help me out..
hi, Can someone suggest me a verilog code for fixed point signed multiplication using 8 bits pl.
verilog simulators provides a few format for data export, such as %b, %d (for decimal). However, in case the vector is a signed number, how we let simulator export utility aware of it and process it correctly? Added after 32 minutes: also, how to fdiaplay the vector representing a real value. How to
Hi, I am pretty new to verilog and was hoping someone could help me out. I am having 2 problems, I am guessing both are related to poor logic. 1) In the example below I am getting warnings that "Warning (10235): verilog HDL Always Construct warning at xxx.v(15): variable "D2" is read inside the Always Construct but isn't in the Always Constr
it is used for signed shifting in verilog 2001
hey I am a student of B-tech . I am doing a project in which i have to use a parallel multiplier. I have to multiply two matrices of 8x8 size and each element is a 16 bit fractional number represented in binary format. I wrote a code in matlab and verilog both but when I matched the result of verilog with matlab, I found big difference between the
Hey, I have a question about verilog. I have a bunch of wires h_in as an input in a module. They represent 640 values of 16 bits. I want to store those into registers, so reg signed h; h <= h_in; h <= h_in; h <= h_in; h <= h_in[3*16:(3+1
i synthesized my code (verilog) containing mainly additions and subtractions and am doing post synthesis simulation in modelsim in modelsim wave i see, instead to obtaining differences of two registers , i am now obtaining difference divide by 2 I am not able to figure out the problem. i even tried re declaring wire resulted by subtraction
Hi , I have 8 numbers like -398.1234 , -14.1898 etc and I have 8 signals generated in the design . I need to compute y = c1* x1 + c2 * x2 .... + c8 *x8 , where c1 , c2 etc are the constants and x1 , x2 are the signals to the block . What is the best way to code this ? since these are floating point numbers , should I multiply them
Hi All In my code im using $readmemh to read hex values from a text file in which alot of the values are negative. verilog is treating them as positive and returning erroneous results. Can someone please help me deal with this problem? I really need to figure out a way to recognize these negative hex values. Please help
It should be noted, that verilog also has a signed data type. But in case of the add and sub operation, it doesn't change anything. The difference between unsigned and two's complement signed is only in the interpretation of the result, the bitvector is the same. You may want to verify this by pencil and paper method. In (...)
Hi, The link( VHDL to verilog (verilog to VHDL) Code Conversion Translation Tools & Tips) may help you find more info on VHDL to verilog (verilog to VHDL) Code Conversion Translation Tools.
Hi there, Recently I was trying to write a verilog Code for Multiplication by 3. Condition-My Input is variable-Unsigned or signed My Multiplier is fixed-3 So if i have -20 as input in binary my output should by -60. and 20 as input my output should be +60. I want to declare only one output that is product and (...)
I want to write a verilog model of a pipelined circuit which its output is y = max{xi, 1signed 2?s-complement integers. plz help. thnx
because division and multiplication can not systhesize in ISE or QUARTUS With Altera Quartus, a divider IP is automaticaly "inferred" from a signed x/y expression in verilog or VHDL. With VHDL, the library IEEE.numeric_std is required for it. I don't know, if there's a similar feature in Xilinx IDE.
if you are using verilog 2001, that's simple problem: wire signed in_a, in_b; wire signed add_out = in_a + in_b; wire signed mul_out = in_a * in_b;
hi, can someone pls convert this verilog code to vhdl code? i need it as fast as possible... thx... this is the code: // 8-bit by 8-bit Baugh-Wooley signed multiplier module BWSM(x, y, p); input x, y; output p; supply0 zero; supply1 one; wire p1; wire p2; wire p3; wire p4; wire p5;
Is $signed() /$unsigned() synthesizable in verilog?
how to write the values of a variable z to a text file in decimal format? i'm using the following verilog code integer fp1; fp1=$fopen("ctq.txt"); $fwrite(fp1,"%d\n",z); but the values of the variable z are still written to the file "ctq" in hexadecimal format ......but i need the values to be written to the file "ctq" in decimal format ho
Hi every one iam looking for a piplined fixed point divider, a generic one that i can choose the size of the dividend and divisor , between 2-32 bits. I found a serial one in opencore, but having difficluty with a a piplined one. If i generate a 32 bit divider using Xilinx coregenerator, will i be able to use it effectively with less than 32
First question, do you know the meaning of the concatenation operator {x,y,z} in verilog? It's simply assembling single bits or bit vectors to a result bit vector. sum5 is adding the original D2 vector and a right shifted D2 value. The right shift is performed by omitting one LSB and adding the MSB for sign extension. Assuming D2 is a signed ent
hello, i need to implement fixed point signed addition of 16 bits at every clock edge for CORDIC algorithm. but the very first addition is overflowing, can anyone tell me how to correct overflow or the method to work with fixed point with overflow. i am using 1 sign bit, 1 integer bit, 14 fraction bits (Q2.14 format).
Hi all, For my complete rtl, Cadence IRUN shows no problems and no warnings. By when I am doing a LEC using Cadence Conformal(rtl VS netlist), then I get two warnings on my rtl which I have no idea how to get rid of. -------------------------------------------- Code where warning is shown..... I get warning msg on the FUNCTION module

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