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79 Threads found on edaboard.com: **Verilog Signed**

hye gaizz,
parameter RED =3'b000; //if assume as 0 round off ~ 0
parameter YELLOW =3'b001; //if assume as 1.2 round off ~1
parameter GREEN =3'b010; //if assume as 2.1 round off ~ 2
parameter BLUE =3'b011; //if assume as 1.7 round off ~ 2
parameter COKLAT =3'b100; //if assume as 0.2 round off ~ 0
parameter BLACK =3'b101; //if assume as 1

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-20-2017 02:08 :: yeppolife92 :: Replies: **7** :: Views: **302**

hello
i am doing a **verilog** project that design a FIR filter.
i generate sin & cos waves with cordic algorithm and apply it to FIR fiter.
i am not sure about response.
this is the code of fir filter:
module FIR_filter(input **signed** x, input clk, output reg **signed** yn);
reg **signed** xn;
wire

ASIC Design Methodologies and Tools (Digital) :: 08-16-2016 22:11 :: elec_eng92 :: Replies: **0** :: Views: **370**

I need some help getting started with writing the following two sort file. Can someone help?
(a) Write a module sortEight, which accepts eight **signed** values and returns eight **signed** values sorted from least to greatest. You should submit one ﬁle for this problem called ?sortEight.sv?. Any additional modules should be inc

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-01-2016 00:03 :: Johnny_freeman78 :: Replies: **2** :: Views: **628**

Hello everyone,
I am trying to design 32 bit binary **signed** digit adder but I am facing issue while writing code for **signed** number. i.e for example if we take number let it be X=10-111 , then I want to represent X as (X+ = 10011 and X-= 11011) then how implement it in **verilog**. please help me.

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-19-2015 10:28 :: aampase :: Replies: **0** :: Views: **560**

Apart from Babylonian method (cannot use this) what other algorithms exist that can be implemented in **verilog**. Requirement is to calculate rms of a series of 32bit **signed** numbers

ASIC Design Methodologies and Tools (Digital) :: 03-11-2015 03:45 :: keyboardcowboy :: Replies: **0** :: Views: **642**

HI,
I am new to system **verilog** and was trying to simulate the following simple program but am not able to understand how the output is beign generated:
module test ();
initial
begin
byte XYZ;
foreach(XYZ)
XYZ=i*100+j;
foreach (XYZ)
begin
$write("%d:",i);
f

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-13-2014 20:36 :: maxxtorr723 :: Replies: **1** :: Views: **550**

0x1FE000 is the correct answer for what you have done.
In **verilog**, the sign of an assignment is determined solely by the right hand side of the equation. In your case you have a **signed** value multiplied with an un**signed** value. The result of (**signed** * un**signed**) is un**signed**. All operands (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-15-2014 23:12 :: rberek :: Replies: **6** :: Views: **1008**

Then you need to read a book on VHDL (or **verilog**)...
c <= a*b;

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-15-2014 16:41 :: ads-ee :: Replies: **2** :: Views: **901**

Hi,
I read the following about **verilog** expression:
Example 4-1
shows two ways to write the expression ?minus 12 divided by 3.? Note
that -12 and -d12 both evaluate to the same bit pattern, but in an
expression -d12 loses its identity as a **signed**, negative number.
108105
I do not know what [

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-07-2014 23:29 :: ruwan2 :: Replies: **0** :: Views: **400**

You have to be very careful when using **signed** arithmetic in **verilog** and System **verilog**. Unless you really understand the way the language treats **signed** values, and especially the way it treats combinations of **signed** and un**signed** values, you can find many ways to hang yourself.
In your (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-10-2014 13:24 :: rberek :: Replies: **3** :: Views: **621**

I have written a **verilog** file that implements some arithmetic operations, I defined my signals as wire **signed** or reg **signed**. when I simulate that on isim simulator it does the operation as specified, with **signed** arithmetic. but when I simulate the same file in modelsim it behaves as if the signals are (...)

ASIC Design Methodologies and Tools (Digital) :: 05-23-2014 21:04 :: 3wais :: Replies: **1** :: Views: **588**

I have to multiply two fractional numbers of 42 bits in **verilog**. I am using the fixed point (Q12.30). Now my result is wrong.
part of my code:
module my_name (out,Clk);
input Clk;
output reg **signed** out; //(Q24.60)
reg **signed** in1; //(Q12.30)
reg **signed** in2; //(Q12.30)
alway

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-24-2013 01:09 :: mohsen p :: Replies: **1** :: Views: **994**

Did you ever consider using the the **verilog** **signed** type?

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-04-2013 17:36 :: FvM :: Replies: **5** :: Views: **1003**

I have a hard time believing that. How did you come to that conclusion?
- - - Updated - - -
Also, you did notice the difference between a vector and a number, right?
I just gave you a single 8-bit **signed** number. No need to add the extra confusion of a vector of **signed** numbers if the problem of the day is "H

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-07-2013 16:22 :: mrflibble :: Replies: **3** :: Views: **474**

Assuming the file in like :
.1
.12
.15
.2
.26
.3
and so on
write code like this
integer in,i,out;
real data;
initial begin
in = $fopen("input.txt,"rb");
out = $fopen("output","w");
if(!in) $display("File Open Error!");
if(!out) $display("File Open Error!");
i = $fscanf(in,"%f",data);
i

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-23-2013 15:56 :: sherif123 :: Replies: **2** :: Views: **1199**

Which file format do you refer to? Any HDL can represent negative numbers, in so far it's surely possible for binary files, if you interprete the data as **signed** numbers. VHDL textio package does support integer and real numbers, both can be negative. I presume, there's a similar option in **verilog**, but I didn't use it for testbenches yet.

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-04-2013 15:49 :: FvM :: Replies: **4** :: Views: **1151**

Hi I have de**signed** a 8-bit counter using **verilog**.
I simulated it using modelsim. counter is performing it's function correctly till the total event at the output reaches 127 (i.e after counting 127 clock cycles)
but after 127 I am getting a value of -128, then -127,126,-125 and so on for each additional clock cycle.
why it is going to -128, why

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-30-2013 06:49 :: kpraneethin007 :: Replies: **2** :: Views: **683**

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-20-2013 07:52 :: charantejvit :: Replies: **1** :: Views: **553**

i need a **verilog** code for 8bit **signed** carry look ahead adder.....
i dont know how to convert the following code... help me soon....:-(
module cla(sum,c_8,a,b,c0);
input a,b;
input c0;
outputsum;
output c_8;
wire p0,p1,p2,p3,p4,p5,p6,p7,g0,g1,g2,g3,g4,g5,g6,g7;
wire c1,c2,c3,c4,c5,c6,c7,c8;
assign p0=a^b,
p1=a^b[

Elementary Electronic Questions :: 12-16-2012 15:23 :: thir :: Replies: **0** :: Views: **6244**

i need to design a multiplier unit..
design idea: only binary inputs representation **signed** representation..can provide a sign bit input..
ie.. if we want to multiply 2 and -3.. input given should be 0010 and 0011(consider 4 bit numbers)..since sign of one of the number is negative..i can give a sign bit input as 1 here.. so i need a program

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-04-2012 09:44 :: kannan1 :: Replies: **0** :: Views: **442**

Hi all,
I am learning **verilog** and this is a module used for read a character:
module file_read()
parameter EOF = -1;
integer file_handle,error,indx;
reg **signed** wide_char;
reg mem;
reg err_str;
initial begin
indx=0;
file_handle = $fopen(?text.txt?,?r?);
error = $ferror(file_handle,err_str);

ASIC Design Methodologies and Tools (Digital) :: 12-03-2012 14:30 :: anhnha :: Replies: **0** :: Views: **2067**

Generally if I declare a variable as integer in **verilog**.. What hardware element the synthesis tool will take that variable.
Thanks in advance

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-04-2012 04:35 :: rknmahesh :: Replies: **5** :: Views: **717**

Declare your signals as **signed**, like so:
input **signed** X;
input **signed** h_0;
input **signed** h_1;
// etc

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-12-2012 01:45 :: mrflibble :: Replies: **4** :: Views: **1284**

As far as I know, **verilog** 2001 has built-in support for this, just using **signed** nets and variables!
Cheers

ASIC Design Methodologies and Tools (Digital) :: 08-04-2012 11:40 :: kingslayer :: Replies: **2** :: Views: **606**

Pleas some one can explain me why in the below code, x0_eq is not equal to x1_eq?
`timescale 10ns/1ns
module test;
reg **signed** x0, x1, x0_shifted, x0_eq, x1_eq;
initial begin
x0 = -27;
x0_shifted = x0 >>> 3;
x0_eq = x0_shifted + x0;
x1 = -27;
x1_eq = (x1 >>> 3) + x1;
#10;
$finish;
end
endmodule

ASIC Design Methodologies and Tools (Digital) :: 06-06-2012 13:18 :: jmarcelold :: Replies: **2** :: Views: **925**

Dear all,
**verilog** 2001 have this functionality for **signed** reg(s) and wire(s).
They work as two's compliment hence are they also synthesizable and will work the same way in-circuit as they do in simulation.

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-01-2012 13:08 :: syedshan :: Replies: **1** :: Views: **695**

hello amir,
In **verilog** 2001, you can now declare **signed** variable and it will automatically be 2's compliment **signed** variable.
wire **signed** inp1; //will take negative values as 2's compliment
reg **signed** inp2; //will take negative values as 2's compliment
assign inp1 = 10000000; // It means -128 (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-02-2012 11:51 :: syedshan :: Replies: **1** :: Views: **752**

check below pdf to work on **signed** and un**signed** in **verilog**.

ASIC Design Methodologies and Tools (Digital) :: 04-24-2012 11:20 :: shanmugaveld :: Replies: **21** :: Views: **4502**

Hi I am trying to do a synthesis of **verilog** code by using RTL compiler .. The code got correctly compiled in modelsim but is giving errors while rtl compilation .. I am using ..
parameter **signed** b0 = 8'b00000011 ;
.. lines in codes to supply constants.. The rtl synthesis is giving the error of b0 being an undeclared variable ! I tried to make

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-19-2012 07:48 :: anishsingh :: Replies: **0** :: Views: **369**

Hi,
How can I convert integer type to **signed** bit vector in **verilog**?
Thanks

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-17-2012 20:53 :: Alka Arora :: Replies: **0** :: Views: **944**

Hi ,
In VHDL we have a function to convert std_logic_vector to **signed** data we have anything like that in **verilog** to convert in to **signed** type in **verilog**.
for example i have wire diff;
I want to convert it into absolute value.
Thanks
Alka

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-13-2012 22:51 :: Alka Arora :: Replies: **3** :: Views: **1739**

The usual number system to represent **signed** quantities in digital computing is two's complement. It's also the method provided by standard VHDL and **verilog** libraries. Other number representations have to be de**signed** by yourself. A **signed** digit representation obviously requires a ternary bit type.
You should tell your (...)

Elementary Electronic Questions :: 03-27-2012 10:35 :: FvM :: Replies: **2** :: Views: **701**

hello,
i need to implement fixed point **signed** addition of 16 bits at every clock edge for CORDIC algorithm. but the very first addition is overflowing, can anyone tell me how to correct overflow or the method to work with fixed point with overflow. i am using 1 sign bit, 1 integer bit, 14 fraction bits (Q2.14 format).

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-13-2011 16:34 :: student13 :: Replies: **0** :: Views: **1267**

Hi every one
iam looking for a piplined fixed point divider, a generic one that i can choose the size of the dividend and divisor , between 2-32 bits. I found a serial one in opencore, but having difficluty with a a piplined one.
If i generate a 32 bit divider using Xilinx coregenerator, will i be able to use it effectively with less than 32

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-10-2011 17:59 :: Hallolo :: Replies: **1** :: Views: **866**

Is $**signed**() /$un**signed**() synthesizable in **verilog**?

ASIC Design Methodologies and Tools (Digital) :: 04-10-2011 21:03 :: gsdeshpande :: Replies: **4** :: Views: **3664**

I am not familiar with VHDL,from **verilog** view,in the "position",**signed** number would not be recognized.
And if you want to implement "abs" function ,here show you an example in **verilog**(16bit):
assign abs_num_diff = num_diff?
(~num_diff + 1'b1) : num_diff;

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-25-2011 07:29 :: yadog :: Replies: **8** :: Views: **1572**

if you are using **verilog** 2001, that's simple problem:
wire **signed** in_a, in_b;
wire **signed** add_out = in_a + in_b;
wire **signed** mul_out = in_a * in_b;

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-21-2011 01:19 :: yanzixuan :: Replies: **4** :: Views: **3253**

Hi Digit0001,
I'm not so familiar with VHDL but in **verilog** I can use **signed** singals to do twos complement multiplication without checking the sign bit.
see example
module tb ();
reg **signed** mcand;
reg **signed** mplier;
wire **signed** result;
initial
begin
// -80 x (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-26-2011 06:09 :: qieda :: Replies: **5** :: Views: **4472**

because division and multiplication can not systhesize in ISE or QUARTUS
With Altera Quartus, a divider IP is automaticaly "inferred" from a **signed** x/y expression in **verilog** or VHDL. With VHDL, the library IEEE.numeric_std is required for it. I don't know, if there's a similar feature in Xilinx IDE.

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-02-2010 09:23 :: FvM :: Replies: **6** :: Views: **7501**

I want to write a **verilog** model of a pipelined circuit which its output is y = max{xi, 1*signed 2?s-complement integers.
plz help. thnx*

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-10-2010 08:10 :: hokmabadi :: Replies: **0** :: Views: **661**

Hi there,
Recently I was trying to write a **verilog** Code for Multiplication by 3.
Condition-My Input is variable-Un**signed** or **signed**
My Multiplier is fixed-3
So if i have -20 as input in binary my output should by -60.
and 20 as input my output should be +60.
I want to declare only one output that is product and (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-05-2010 19:11 :: er.twi.fb :: Replies: **4** :: Views: **3599**

It should be noted, that **verilog** also has a **signed** data type. But in case of the add and sub operation, it doesn't change anything. The difference between un**signed** and two's complement **signed** is only in the interpretation of the result, the bitvector is the same. You may want to verify this by pencil and paper method.
In (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-02-2010 10:04 :: FvM :: Replies: **1** :: Views: **1748**

When dealing with negative numbers in **verilog** (either decimal or hex) you must indicate explicitly that you are using **signed** numbers. To do that you just have to declare your variables as **signed**:
"reg **signed** var"
Do the same for input or output signals:
"input **signed** var"

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-14-2010 17:16 :: fcfusion :: Replies: **2** :: Views: **1616**

Hi ,
I have 8 numbers like -398.1234 , -14.1898 etc and I have 8 signals generated in the design .
I need to compute
y = c1* x1 + c2 * x2 .... + c8 *x8 ,
where c1 , c2 etc are the constants and x1 , x2 are the signals to the block .
What is the best way to code this ?
since these are floating point numbers , shoul

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-06-2010 08:35 :: yanzixuan :: Replies: **2** :: Views: **4698**

i synthesized my code (**verilog**) containing mainly additions and subtractions and am doing post synthesis simulation in modelsim
in modelsim wave i see,
instead to obtaining differences of two registers , i am now obtaining difference divide by 2
I am not able to figure out the problem.
i even tried re declaring wire resulted by subtraction

ASIC Design Methodologies and Tools (Digital) :: 05-21-2010 06:51 :: Aimerbhat :: Replies: **1** :: Views: **1009**

hey
I am a student of B-tech . I am doing a project in which i have to use a parallel multiplier. I have to multiply two matrices of 8x8 size and each element is a 16 bit fractional number represented in binary format. I wrote a code in matlab and **verilog** both but when I matched the result of **verilog** with matlab, I found big difference between the

Digital Signal Processing :: 05-02-2010 14:52 :: magnanimus :: Replies: **4** :: Views: **12021**

Microcontrollers :: 03-13-2010 13:10 :: amraldo :: Replies: **9** :: Views: **1498**

it is used for **signed** shifting in **verilog** 2001

ASIC Design Methodologies and Tools (Digital) :: 03-09-2010 11:16 :: kalyansumankv :: Replies: **3** :: Views: **2474**

Hi, I am pretty new to **verilog** and was hoping someone could help me out.
I am having 2 problems, I am guessing both are related to poor logic.
1) In the example below I am getting warnings that "Warning (10235): **verilog** HDL Always Construct warning at xxx.v(15): variable "D2" is read inside the Always Construct but isn't in the Always Constr

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-21-2010 04:46 :: chasef4 :: Replies: **3** :: Views: **2400**

Digital Signal Processing :: 01-05-2010 20:49 :: neoflash :: Replies: **1** :: Views: **1579**

Last searching phrases:

countdown counter | circular microstrip | soc install | ic5141 rhel4 | plane wave code | graduates | unused pins | clock dividers | jitter buffer | layer overlap

countdown counter | circular microstrip | soc install | ic5141 rhel4 | plane wave code | graduates | unused pins | clock dividers | jitter buffer | layer overlap