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you need to read the datasheet first what is the output format. Basically, it is in binary, either in serial or parallel form. To display on seven segment display, you need to convert the format from binary to decimal form, use the circuit such as binary to decimal (bcd) conversion circuit. You can implement it with FPGA. Search the web for vhdl
Hi there, please advice on how is the most effective way to change 8-bits binary no. to bcd by using vhdl. thank you.
Here is verilog code for 16 bit bcd up counter translate this to vhdl! Hope this helps! module bcd_count ( // Outputs count, // Inputs clk, reset_n ); input clk, reset_n; output count; reg count; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin count <=
hi, is there someone who knows where to find or who has some verilog/vhdl implementations of a (iterative) bcd multiplier ? thanks, avt
Hello to all, I?m newbie in vhdl programming on FPGA. I need help from all of you out there. Right now I try to write a code for 2-digit bcd down Counter, LCD display message and synchronization between both of them. For 2-digit bcd down counter, here?s my code library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
hi I need how design code vhdl for bcd adder 4 digit(16 bit) ?
Do you mean 16-bit bcd adder??? If yes see the link below... Its in verilog you can convert it into vhdl ..
hmm....can you xplain it more beter? im having problem on making a vhdl code, coz i dont know the structure.... can you post the structure of it?/ thnx in advance In terms of structure, it's up to the coder. There are many ways to do it. But I feel as though you are seeking HDl code to solve your problem. You can fin
vhdl supports the real data type directly. No need for conversion. However, many synthesis tools don't support real, but that's a different issue. Some tools provide various workarounds (such as core libraries) for doing floating point calculations. Or you can scale all your arithmetic algorithms so they fit conveniently into integers or fixed-p
I have written a structural code vhdl and tried to compile it. Code: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux_8X8 is port(A,B: in std_logic_vector(7 downto 0); start, reset, clk: in std_logic; result: buffer std_logic_vector(15 downto 0); leds: out std_logic_vector(1 to 7); done_
Hi, I need to implement a simple vhdl frequency counter for a school project. Must be 4 multiplexed digits. (the FPGA as few macrocells). I know how to implement the counter and the bcd to seven segment. is the multiplexing and puting things togheter that i need help. Can anyone point me to an example? Must be very simple. Thank you in
Hello - I am somewhat new to vhdl, but I have some past experience with discrete digital design. I would like to take a bcd number that is in the std_logic_vector format and convert it into ieee single float format in order to use the number as an input to the Xilinx Floating Point IP Core. I am starting in bcd because it was (...)
I'm from Brazil, but I think I can help you. You can describe a frequency divider for the 50 Mhz oscilator on the board. To download a vhdl code in the FPGA, you can read the ISE Quick Start Tutorial that you can find here: ∫Good Luck.dx
vhdl coding tips and tricks: vhdl code for bcd to 7-segment display converter Lab 4 - bcd to Seven-Segment Decoder refer this show your code...
Hi I have a vhdl code counter that counts in binary from 6 to 88 then it rolls over to count down from 88 to 6. Now i want to do the same counter but instead of counting in binary i need it to count in bcd. can i show the count values in quartus in bcd? if not please any help how can i do that? thank u in advance.
Whats wrong with fixed point packages? there is a Xilinx version here: vhdl-2008 Support library But whats wrong with this code? temp0 := resize(Input1, temp0'length) * 2**12; temp0 := temp0 * 3300; output <= temp0(23 downto 12);
hi i would like to include this functions in a package and use it in any other design can u please help? function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is variable i : integer:=0; variable bcd : std_logic_vector(11 downto 0) := (others => '0'); variable bint : std_logic_vector(7 downto 0) := bin;
I am trying to write the vhdl code for a Timing Genarator Chip : in the vhdl code i have to incorporate a code for the 16 Bit bcd(Binary Coded Decimal) Counter i.e. 4 Decades , i tried a lot but unable to figure it out how to get it working... as the 16 bit bcd counter can count from 0 to 9999 ,for the first 9 clock pulses (...)
Hi, Define your input and output seperately, thenn define a new variable using inputs by concatenation (the operator &) here is one
Hi, I need to develop a vhdl code for 9 bit binary to bcd number. I searched in internet and find code for converting 8 bit and 10 bit numbers Can anyone help me in writing the code for this 9 bit binary number
Hey Barry; I thought you could interpret it should be in vhdl... As I have posted it under FPGA thread..... As by far people program it in vhdl... well its FPGA...
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments.... For FPGA design, what I have used synthesis tools(only to synthesis vhdl code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar It is only my personal opinion...
Can someone give me links to documentation and foundries proposing bcd-processes (biploar/cmos/dmos)?
hi all just go to aldec website and you can download free tutrial presentation for both verilog and vhdl. EcraZ [ This Message was edited by: EcraZ on 2001-11-22
I am a student from Harbin China. Now I am building a behavioral model of a Direct Sequence Spread Spectrum Communication system using vhdl-AMS. So i want to know where can I find some example similar to that or something that may give help to me. Can you give me some advices. Thank you! [ This Message was edited by: flybear on
Hi vhdl QUICK Reference Guide Ready for onboard prints tnx Uploaded file: vhdlref.pdf
where to get test bench with vhdl for SDH chip?
Hi The vhdl Golden Reference Guide A 136 pps ebook. tnx Uploaded file: vhdl-golden-reference.pdf ************************************************************** Please don't reply unless you have useful information to add on this post. Thanks ! (No Me-too's, no Thanks-you's, etc ... use
Hi Here is the vhdl code for 8051 MC. tnx Uploaded file: 8051 in vhdl.zip
Hi LEON is a synthesisable vhdl model of a 32-bit SPARC* compatible processor, developed by the European Space Agency (ESA) for future space missions. To promote the SPARC architecture and enable development of system-on-a-chip (SOC) devices using SPARC cores, ESA is making the full source code freely available under the GNU LGPL license. LEON
Hi vhdl Language reference manual. latest edition. regards _________________ ***************************************** Please don't reply unless you have useful information to add on this post. Any other replies are always welcome via PM. ***************************************** [ This Message was edited by: KARLZ on
This reply is for those who will be reading this thread ... You can find/download free vhdl, Verilog testbench generators from . Other free utilities available in this site are, Verilog netlist parser, RTL uniquifier. All these utilities are platform independent ( Windows, Linux, Solaris ) as these are imp
Hi These materials are made available for ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech. This text focuses on presenting the basic features of the vhdl language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by fami
Thank you !! On 2002-03-05 02:12, mexico_mike wrote: Anyone interested in a single entity vhdl testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this. Uploaded file: [url="./uploads/tb_g
Hi Would you please upload IEEE Standards for verilog and vhdl to this place. NOTE!!!!: 1. If you have uploaded files in some other boards, please leave a URL pointer only. 2. Please rename the files before uploading by the a definitive words to distingush files from each other. It seems that the forum replaces every newer file with
IMHO, I think Verilog will probably become increasingly dominant in the future. Realistically though, vhdl is here to stay for a long time. This means several things. 1) You still need to own and know how to use vhdl tools. 2) You still need to know vhdl
Anyone has a DSP core in vhdl or Verilog? Prefer TI but anyone will do. ASIC
Would anyone share the RS232 vhdl code ? If you have RS232 test program , please share. Thanks a lot.
On 2002-04-06 09:47, antipattern wrote: How about the Ben Cohen's books and the "vhdl Coding and Logic Synthesis with Synopsys" -- by Weng Fook Lee? Thanks, Where can I find these books?
Hi Tutorials for vhdl and Verilog. HDL Synthesis for FPGAs: Design Guide (PDF 2MB) SystemC -- Technical Papers Cypress: Programmable Logic: vhdl Page Cypress: Design Resources : Technical Articles Logic Synthesis with vhdl System Synthesis vhdl SYNTHESIS TUTORIAL vhdl Coding Style manual (...)
All of four blocks are sensitivity list incomplete. vhdl is a strong type language, don't you get a error message about that when you compile the codes?
Hi This object of this course is to introduce the student to more of the vhdl modeling language than what has been covered in previous courses. 1. -> t tnx
Hi P1076.2 P1076.3 P1076.4 ieee_1164 mathpack synopsys 1. -> t tnx
Hi 1. -> t tnx
mates..this is what iam crying for last 6 months.. systemgenerator will give vhdl code as well as testbench codes for matlab scripts specific for dsp related apps,, can anyone provide a full version of system generator
Hi, everybody, I am seeking cache controller vhdl example, I hope some good guy can give me hint or tell me where I can find it. It is better a standalone module, simple. Thanks :P
here is a link to comp.lang.vhdl newsgroup about the necessary of the sensitivity list. very interesting. :arrow:
Can any body help me if you have vhdl code for BFSK or even clear flowchart Thanks
hi,all Is it possible that Vera work with NC-verilog/vhdl ? Refer to Vera's documents. There is a step-by-step guide to compile the PLI for NC-Verilog.
Hi guys! I need tha vhdl of the PCI LogiCORE interface from Xilinx.. could you help me??? Tnx a lot LEron