Search Engine www.edaboard.com

Vhdl Bcd

Add Question

38 Threads found on edaboard.com: Vhdl Bcd
Hi there, please advice on how is the most effective way to change 8-bits binary no. to bcd by using vhdl. thank you.
any code available ?? on vhdl and also tutorial points will be given....... ty in advance
ill be coding it on vhdl, can you help me find the specificatoin of it??
Here is verilog code for 16 bit bcd up counter translate this to vhdl! Hope this helps! module bcd_count ( // Outputs count, // Inputs clk, reset_n ); input clk, reset_n; output count; reg count; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin count <=
hi, is there someone who knows where to find or who has some verilog/vhdl implementations of a (iterative) bcd multiplier ? thanks, avt
hi i have to perform real num addition. i will use the single precision format. can i give the input as a real num for ex:4.5.. is this possible in vhdl can any one help me how to convert real num into binary.. using vhdl i am not getting how to proceed
dear siowyein... its very diffficult to understand your code... are you getting your error in simulation or synthesis... what simulator are you using...? i was able to simulate and synthesis your code... to tell you something your code is very inefficient...you are trying to realise your logic... you didnt realise that your code
hi echo, thanks for the waveform pdf....... and for deepak... please send me the logic or vhdl code for the fsm.... thanks..
you need to read the datasheet first what is the output format. Basically, it is in binary, either in serial or parallel form. To display on seven segment display, you need to convert the format from binary to decimal form, use the circuit such as binary to decimal (bcd) conversion circuit. You can implement it with FPGA. Search the web for vhdl
I have written a structural code vhdl and tried to compile it. Code: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux_8X8 is port(A,B: in std_logic_vector(7 downto 0); start, reset, clk: in std_logic; result: buffer std_logic_vector(15 downto 0); leds: out std_logic_vector(1 to 7); done_
Hello to all, I?m newbie in vhdl programming on FPGA. I need help from all of you out there. Right now I try to write a code for 2-digit bcd down Counter, LCD display message and synchronization between both of them. For 2-digit bcd down counter, here?s my code library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
Hi, I need to implement a simple vhdl frequency counter for a school project. Must be 4 multiplexed digits. (the FPGA as few macrocells). I know how to implement the counter and the bcd to seven segment. is the multiplexing and puting things togheter that i need help. Can anyone point me to an example? Must be very simple. Thank you in
Hello - I am somewhat new to vhdl, but I have some past experience with discrete digital design. I would like to take a bcd number that is in the std_logic_vector format and convert it into ieee single float format in order to use the number as an input to the Xilinx Floating Point IP Core. I am starting in bcd because it was (...)
I'm from Brazil, but I think I can help you. You can describe a frequency divider for the 50 Mhz oscilator on the board. To download a vhdl code in the FPGA, you can read the ISE Quick Start Tutorial that you can find here: ∫Good Luck.dx
Firstly, I would like to congratulate you on getting your code to work. Unfortunantly, its generally not reccomended to write code like this. For college projects, its not bad though. The biggest issue is the clock divider. For FPGA's, you have some dedicated clock resources. The fancier you get with code like above, the les
Hii friends, this site is very useful for the students and this is the first time I am posting and please make me happy....... For your design project you will be creating a simple calculator. The calculator has a keypad as its input. The keypad has the decimal numbers 0 ? 9, clear,=, + and -. You will only be implementing addition and subtracti
How do i display the values 0 to 9 on the 7-segment display and whenever the count is 1, 3 or 5, a Led will turn on. using vhdl NEED HELP!! i was able to display the values 0to9 on the 7 segment display. But the important part is when the count is 1, 3 or 5, the led has to light up. What is need is: the code to light up led
vhdl coding tips and tricks: vhdl code for bcd to 7-segment display converter Lab 4 - bcd to Seven-Segment Decoder refer this show your code...
Hi I have a vhdl code counter that counts in binary from 6 to 88 then it rolls over to count down from 88 to 6. Now i want to do the same counter but instead of counting in binary i need it to count in bcd. can i show the count values in quartus in bcd? if not please any help how can i do that? thank u in advance.
Whats wrong with fixed point packages? there is a Xilinx version here: vhdl-2008 Support library But whats wrong with this code? temp0 := resize(Input1, temp0'length) * 2**12; temp0 := temp0 * 3300; output <= temp0(23 downto 12);
What's you particularly question? I see, that you have been able to copy the popular "double dabble" code from the internet. (Reference in ) As far as I see, it's a syntactically correct vhdl function. I assume, it will serve it's purpose. P.S.: In addition, you would want to add a standard package
I am trying to write the vhdl code for a Timing Genarator Chip : in the vhdl code i have to incorporate a code for the 16 Bit bcd(Binary Coded Decimal) Counter i.e. 4 Decades , i tried a lot but unable to figure it out how to get it working... as the 16 bit bcd counter can count from 0 to 9999 ,for the first 9 clock pulses (...)
Hi all, In the process of digital to analog conversion, the thermometer code output, corresponding to the digital value of the input signal, activates the unit value of the analog entities (which may be current or voltage sources). The analog output is the summation of all those activated analog entities. Please can any one help me or give me
Hi all, In the process of digital to analog conversion, the thermometer code output, corresponding to the digital value of the input signal, activates the unit value of the analog entities (which may be current or voltage sources). The analog output is the summation of all those activated analog entities. Please can any one help me or give me
Okay, at least we know you tried. Unfortunately, I don't know Verilog, just vhdl. But I suspect the problem is in your second block (always@(reg_cnt)...) If Verilog is like vhdl, then at least one of the elements in the sensitivity need to CHANGE in order for the process to run. (At least in simulation). There is nothing to guarantee that reg_c
Hi, Define your input and output seperately, thenn define a new variable using inputs by concatenation (the operator &) here is one
Hi, I need to develop a vhdl code for 9 bit binary to bcd number. I searched in internet and find code for converting 8 bit and 10 bit numbers Can anyone help me in writing the code for this 9 bit binary number
What are you trying to divide, signed? unsigned? integer? Yes, you CAN use "/" in vhdl; whether you can synthesis this depends on your tools. You can also instantiate IP that will perform division.
hi, division algorithms are complex.if u can afford some errors(apprximation to values) u can just use shift right function in vhdl(shr function). I beg to differ here ... if the number is in binary then shr will produce a value way off limit. If the represantation is in bcd that's cake walk ... just shift it by 4* (no. of di
How about using a 64Kx35 ROM? Feed the 16-bit number into the ROM address, and then connect the 35 outputs directly to the segment pins of the five digits (plus some current limiting resistors). Or, with a little extra ingenuity, use a 512Kx7 ROM plus a few CMOS chips to scan the digits. How about using an FPGA or CPLD? You could then design the
you can use vhdl simili from symphony eda. search for it in google. Kr, Avi
Hi guys, I having trouble compiling my vhdl code below on quartus: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux_8X8 is port(A,B: in std_logic_vector(7 downto 0); start, reset, clk: in std_logic; y: buffer std_logic_vector(15 downto 0); leds: out std_logic_vector(1 to 7); done_fl
Hi to everyone, I have very good knowledge in both VErilog and vhdl, i have worked with I2C SPI protocol, i am thinking to do more good projects in the forntend, if i start search the net i m getting the same topics like I2c and SPI, i m interested to learn more new things in fornt end , plz suggest me some good valuable projects. Regards Ka
few useful links vhdl code for bcd to 7-segment decoder vhdl coding tips and tricks: vhdl code for bcd to 7-segment display converter
Hi, I'm new in vhdl programming. I want to make a 8 bit binary to bcd conversion and I have found the following double dabble algoritm on the net: function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is variable i : integer:=0; variable bcd : std_logic_vector(11 downto 0) := (others => '0'); (...)
check out my code for displaying no. on 7 seg: All About vhdl Codes, PCB Designing and AVR: bcd to seven seg decoder in vhdl(synthesizable) a simple 0 to 9999 counter on 7 seg : All About vhdl Codes, PCB
hi all,,,,,,,,i made a 640x480 VGA controller in vhdl using Spartan-3. AND, i could display characters too. now, i'm trying to display a digital clock on screen. i tried to make bcd counter and address variables to the characters , but it didn't work. the question is, how i can combine the vga controller code and clock together , and addres
hi all i need vhdl code for 0-99 bcd counter 7-seg display code Changed by pressing the Button tanx