8 Threads found on edaboard.com: Vhdl Code For 8 Bit Microprocessor
i need vhdl code for 8 bit microprocessor,i am getting problem in timing and control unit....and how to synchronize all the components in microprocessor...
if any one have please mail .....
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.04.2006 02:50 :: :: Replies: 8 :: Views: 7151
Read "vhdl programming by example" It is a very good book, The last 4 chapters is talking about designing a microprocessor using vhdl.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.11.2006 13:56 :: yasser_shoukry :: Replies: 1 :: Views: 992
I had written a vhdl code for 16 bit microprocessor and i would like to implement this on CPLD. And i would like to know can i made my own PCB or i have to purchase the ready-made board. If it is possible what are the necessary interfacing devices.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.11.2011 05:27 :: vimalpandey :: Replies: 11 :: Views: 928
i need vhdl code for 8-bit microprocessor
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.02.2012 06:45 :: vishal_meshram1087 :: Replies: 1 :: Views: 409
Under computer architecture course, I've to design a microprocessor with 8 bit data and 16 bit address ..minium 20 instructions and at least 2 mode to address. I need to write RTL for instructions and there timing diagrams and block diagram of the circuit.
Is there any software which (...)
Embedded Systems and Real-Time OS :: 12.12.2005 09:09 :: buts101 :: Replies: 4 :: Views: 1209
I want to make a compiler for a microprocessor I am doing in vhdl, a have the instruction set a I just want that the compiler take a txt file with the program , and give an another txt file with machine code. I think visual basic can make the interface part but it also can do the scaner part of the txt file and (...)
PC Programming and Interfacing :: 02.12.2005 14:07 :: snaider :: Replies: 4 :: Views: 1674
vhdl also will pick up cnt <= cnt mod 8; This will work for power-of-two sized counters. Then there is no logic for the comparison. Really, the synthesizer might also notice that already.
for other sizes, you can also play some small games. eg, for a 10 element count, choose 1100 - 0011 - 0100 - 0101 - (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.04.2012 22:32 :: permute :: Replies: 8 :: Views: 327
well you have written a very high level code, thats way its taking time. ireg is written in very high-level description, that might also causing problem. split the design into datapath and control-unit. draw a datapath block diagram of your core -- showing alu, register file, temp-regs, data_ram and code-rom, muxes (where needed) and their intercon
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.03.2006 21:52 :: umairsiddiqui :: Replies: 1 :: Views: 1207