69 Threads found on edaboard.com: Vhdl Code For Adc
i need code vhdl code or verilog code for adc ans DAC please help me ..
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.09.2007 01:26 :: rajakash :: Replies: 3 :: Views: 3337
you can check the function hdl library which is provided by cadence. this library has the sample code for a 8-bit adc and its inll and dnl test code. for the using of ahdl or vhdl-a you can check the online manual
Analog IC Design and Layout :: 11.03.2007 14:56 :: pk3316 :: Replies: 2 :: Views: 1567
There is a version of vhdl called vhdl AMS. It can be used for mixed signal design. Therefore adc can easily modeled by using vhdl AMS.
Analog IC Design and Layout :: 17.05.2008 03:05 :: electronics_sky :: Replies: 2 :: Views: 1901
I want vhdl code for interfacing adc (SP774BT) to FPGA>>>
I have attached my datasheet
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.03.2009 04:37 :: hrushi53 :: Replies: 0 :: Views: 1121
I am designing a circuit that will convert 12V signal into digital through a Comparator and that needs to be read by FPGA.
(1) If I don't use a common GND for the comparator and the FPGA, do I have to use Differantial inputs?
(2) Which IO Standard do I use, and where can I get their specifications
(3) Can someone advise me o
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.05.2009 07:07 :: roddyalan :: Replies: 0 :: Views: 1224
I need vhdl code for interfacing on board 8 bit adc-DAC to FPGA SPARTAN 2
pl. help me
Hobby Circuits and Small Projects Problems :: 27.10.2010 05:37 :: Anuja Diggikar :: Replies: 0 :: Views: 2585
I am doing project on BPSK Modulation and demodulation implementation on FPGA Spartan 3E.
if you help us it will grateful, we need vhdl code adc/DAC interface with Spartan 3E.
Regards & thanks
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.02.2012 05:48 :: Abhi_7 :: Replies: 2 :: Views: 2691
i need a vhdl code for fifo memory to store binary values from a high speed 8 bit resolution adc. can help me give the code and the ucf file for implementing it on spartan 6 sp605( fpga kit).??
you can automatically generate it with xilinx core generator (coregen) you (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.07.2013 02:48 :: aruipksni :: Replies: 1 :: Views: 583
Hi, i am new to vhdl. I am provided with a spartan3 fpga. After sourcing for an adc(10 bit), i have selected the microchip (MCP3002) which requires SPI.
I am a bit confused on how to start. I've tried reading vhdl code but it doesnt make sense to me. On the adc datasheets, i know that i (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.09.2008 08:54 :: ombadei :: Replies: 0 :: Views: 1580
can someone pls provide me with the vhdl code to interface adc0804 (8 bit parallel adc) with Cyclone II DE1 FPGA? this is urgent pls:cry:
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.04.2010 05:05 :: dante_t :: Replies: 0 :: Views: 1549
You mean to create an adc peripheral inside the FPGA using vhdl... that is not possible,
you can only use vhdl to control an external adc and read the digital result.
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.02.2011 04:20 :: alexan_e :: Replies: 8 :: Views: 1056
can any one suggest me with a simplified vhdl code for interfacing spartan 6(sp605) with an ic adc 0804?
adc 0804 data sheet.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.07.2013 03:17 :: aruipksni :: Replies: 1 :: Views: 269
finally i get the waveform !!!! anyone here can guide me for the next progress that is how to get the waveform for adc using visual elite??? any component can replace it?? example 8 bit counter?? need someone to guide me...
oh ya... today i was try to get the octal latch waveform and the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.09.2005 14:27 :: petronas23 :: Replies: 0 :: Views: 518
I'm learning vhdl .i want an example of vhdl code for connecting a flash adc
to the FPGA.
thanks a lot
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.04.2006 16:34 :: aria62 :: Replies: 8 :: Views: 12324
can anyone send a code(vhdl)
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.06.2007 09:56 :: rajakash :: Replies: 0 :: Views: 532
Some months ago, I wrote a simple crude Verilog module (sorry not vhdl) that displays "Hello World!" on the LCD of the Xilinx Spartan-3E Starter Kit. Maybe it will help you. Look in this long discussion for my message dated 07 June 2007:
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.04.2008 18:42 :: echo47 :: Replies: 3 :: Views: 3351
I have constructed the vhdl code for master(FPGA) and slave (adc).
What are you trying to achieve? If you want to control the adc, you have to design a SPI master interface. A vhdl code for the slave would be needed only to simulate the slave's behaviour. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.12.2009 08:17 :: FvM :: Replies: 10 :: Views: 2135
hi, i want to interface adc with a cpld ,how can i do the same
Electronic Elementary Questions :: 14.12.2009 04:07 :: shrirangB :: Replies: 1 :: Views: 1263
I want to use the adc on spartan 3e kit. I think I need to use SPI interface to connect the adc to the FPGA. I wonder if I can find a vhdl source code for using adc with SPI interface. Please help me...
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.04.2010 08:54 :: ytmm :: Replies: 6 :: Views: 3542
I cannot get the following code to produce the correct results of a subtraction and I'm not sure what is wrong with it. Current is an input from an adc that is in two's complement form. The clk is the same for both the adc so that I should be clocking in a new sample at the same rate of the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.08.2010 11:20 :: rawbus :: Replies: 8 :: Views: 1796
Please help me regarding vhdl code to interface adc0804( the 8-bit adc) to FPGA .
please send the vhdl code as early as possible.
I am waiting for ur reply.
pls its urgent.
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.01.2011 12:10 :: rajnaren5 :: Replies: 0 :: Views: 1198
rnx for replay my a/d is 14bit and i want use fft on my signal but i cant write vhdl code for saving signal on my flash and read fron it
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.09.2011 12:34 :: hamid169 :: Replies: 4 :: Views: 365
mates..this is what iam crying for last 6 months..
systemgenerator will give vhdl code as well as testbench codes for matlab scripts specific for dsp related apps,,
can anyone provide a full version of system generator
PC Programming and Interfacing :: 15.07.2002 09:52 :: synq :: Replies: 32 :: Views: 15009
Can I use certian VHL attribute to direct the synthesizer to assign certain Input or output pin to certain pin location on the target FPGA ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.07.2003 06:47 :: Tetra :: Replies: 7 :: Views: 3441
One more thought would bring up this:
What if the digital guy give us the Verilog / vhdl code,
what can we do about it?
Analog IC Design and Layout :: 28.02.2006 22:46 :: jcpu :: Replies: 24 :: Views: 8854
Hi,Can you help me for something?
I want to use the fpga interface for the dual-slope A/D converter using TC7109CPL
my analog input is Sine Wave signal so...
How is design vhdl code to read the amplitute of sine signal? can you suggest me?
thank you a lot!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.07.2006 16:36 :: nansity :: Replies: 1 :: Views: 819
hi!, I recently started using system generator of version 8.2 with matlab 7.1. While generating for blocks related to communication sets in simulink(ver 6) using xilinx system generator 8.2, I require adc and DAC block set, for which Xilinx system generator only has certain xilinx default "xpc" target based adc and dac (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.01.2008 04:11 :: xtcx :: Replies: 2 :: Views: 3767
SA register can be made as a simple shift register which shifts a logic HIGH from MSB flop to LSB flop. Also it stores the current comparator input to the corresponding flop.
This should be very easy to implement.. either writing vhdl code or manual design...
Analog Circuit Design :: 14.02.2008 23:11 :: fredflinstone :: Replies: 18 :: Views: 11172
One way to do that, you could create an initialized array of registers in your vhdl, and the data will be stored in the FPGA's internal memory like a ROM. If you are using Xilinx, there's sample vhdl code in the XST User Guide section "Initializing RAM Directly in HDL code".
Depending on which tools you are using, other (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.03.2008 14:25 :: echo47 :: Replies: 6 :: Views: 885
I have to control analog signals using a board Virtex-5 DSP !!!!
Somebody has source code for interfacing with adc AC97 codec chip(AD1981B) in vhdl?
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.01.2009 06:40 :: swapnil_vlsi :: Replies: 1 :: Views: 1428
Hi, i am working on the topic adc to FPGA interface, i am using 1674adc n EPM7160s
FPGA. Can u send me the vhdl coding for the same.
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.11.2009 08:11 :: shivaprasadbellad :: Replies: 2 :: Views: 831
Hi, i am a beginner in designing using vhdl. I need to construct interconnection between adc(ADS7861 from Texas) and FPGA DE2 board. I have been told to use a SPI --- a serial to parallel SPi interface between adc and FPGA. I have constructed the vhdl code for master(FPGA) and slave (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.12.2009 11:40 :: LF_LF :: Replies: 0 :: Views: 698
I am constructing an vhdl code for clock divider and specification of 2 pins.
I need to trigger 2 pins using DE2 board for 1 clock cycle(auto trigger down itself after 1 clock cycle).
However, i have no idea how to convert that output of my clock divider for the clock of my pin (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.01.2010 00:01 :: LF_LF :: Replies: 12 :: Views: 2091
i need to implement a sigma delta adc with 12 bit resolution at the output.
The sigma delta design has the modulator part followed by the digital decimation filter.
i have constructed the modulator part in "system vision"
now i require the DIGITAL DECIMATION FILTER part in vhdl to complete the design.
Can somebody help me in how to construct th
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.01.2010 09:58 :: rakesh045 :: Replies: 3 :: Views: 2881
i want to interface on board adc to spartan 3E startkit with computer inbuilt signal, using vhdlcode...............
.........If any one have it's vhdl or Verilog code please
give me..........if any document for implementing this
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.07.2011 16:25 :: firstname.lastname@example.org :: Replies: 4 :: Views: 1020
i am in need of simple adc code in vhdl with analog input at port grater the bit better it will be
can anybody help me ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.09.2011 07:53 :: cheetha :: Replies: 8 :: Views: 1726
I am trying to configure an adc using an FPGA. I can read the default values from the adc register properly, but I'm unable to write to those registers.
The fpga clock is 48 MHz and serial clock for the adc is 8 MHz. The vhdl code that I've written is given below.
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.04.2012 22:25 :: aroy :: Replies: 4 :: Views: 487
I need to write vhdl code for ADS8558.
Its a 16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL so far I am unable to figure out how should I do it.
I have Xilinix ISE 10.1 and the board I am using is Virtex2PRo.
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.05.2012 08:22 :: ishailesh :: Replies: 10 :: Views: 2909
You can't sample with vhdl code; but you can read the output of an adc with vhdl code. Yes, you CAN sample with an FPGA card if it has an on-board adc!!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.08.2012 18:21 :: barry :: Replies: 36 :: Views: 1928
I am trying to understand a design code where operation starts after trigger, I have a little propblem
in understanding WHY a certain operation is done in the code...
trigger_to_fpga : in std_logic; -- external trigger to start data capture from adc
signal ext_trigg_pipe :std_logic_vec
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.02.2013 02:45 :: syedshan :: Replies: 3 :: Views: 237
You are asking how to write a SPI master in vhdl.
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.04.2013 03:42 :: FvM :: Replies: 2 :: Views: 301
I should design a digital filter of first order adc Sigma-Delta converter with 8 bits, an over sampling ratio of 64 (OSR = 64),and sampling frequency of 10.24MHz.I make it with MAtLAB SIMULINK as shown in this
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.06.2013 12:43 :: fasto2008 :: Replies: 6 :: Views: 746
Hi bekirhakan and Vonn,
Yes you can use vhdl to program the digilent board. Try ISE webpack (free) at xilinx website. With this soft and one paralel cable you will be able to program the board with vhdl code.
bekirhakan could you tell us more about conversion to/from LVTTL-->CMOS??
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.11.2003 16:00 :: jonatan :: Replies: 9 :: Views: 6499
Im also interested in building a DSO.
I've found this site that uses adc+FPGA+PC
The general idea is clear and has some vhdl code.
Analog input is not completely posted.
There is also another post in this forum with more info.
Hope this help!
Hobby Circuits and Small Projects Problems :: 13.04.2004 09:08 :: martingn :: Replies: 6 :: Views: 1280
I know How is the best method to implement but I try to find a prepared code for these; vhdl or C
Digital Signal Processing :: 11.04.2006 03:30 :: agha :: Replies: 4 :: Views: 1472
Hi frendz I need to design an Ultrasonic range finder.
Plz help as i am an amateur wid vhdl. I am uploading the diagram and for more information plz ask me. Also it doesnt have to be very
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.11.2006 03:04 :: greprac :: Replies: 6 :: Views: 1557
use fdatool in matlab to design ur filter quantize it to the required data format and generate a verilog/vhdl code + test bench. it would be really simpler to verify.
The decimation filter is a multistage filter.
Because I design each stage separately.
How the testbench of the decimation filter be
Digital Signal Processing :: 24.04.2007 04:51 :: corgan :: Replies: 7 :: Views: 2174
I'm a bit new to fpga-s. I need help or sample code (vhdl if possible) for the A/D module.
I need a controller that initiates conversion and stores the data in a register or variable.
If you can, please help!
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.09.2007 17:22 :: Psyfusion :: Replies: 2 :: Views: 2454
use de2 board from altera or any board which is having adc for conversion or connect the external adc using ide cable .
this is hw set-up !
for code you first read the syn oriented book .
tell me do you have basic about vhdl , your qualification , project for what ? std
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.10.2008 12:45 :: manish12 :: Replies: 1 :: Views: 3037
I HAVEN'T BEEN USING THIS XILINX TOOL for quite some time and i decided to re-learn it with version 10 .And wow HOW MUCH THIS TOOL has got sofisticated. There is so much posibilities to design complex systems . I'm trying to completly design software defied radio and import some of the vhdl code to M black boxes .
i'm having so much FUN (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.01.2009 16:55 :: eltonjohn :: Replies: 7 :: Views: 870