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Vhdl Code For Adc

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34 Threads found on edaboard.com: Vhdl Code For Adc
Hello.I have a time-based analog to digital converter.This converter consist of 3 parts.voltage to time(VTC) and time to digital(TDC) and digital to binary(T2B).Now I want to measure conversion time of this converter.also I simulate VTC in Hspice and I simulate TDC and T2B in vhdl code.Now how to to measure conversion time of this converter?
I am trying to build a basic thermometer with LM35 sensor and adc0804. I am also using basys2 fpga. The problem is the LSB of adc keeps blinking and i can't get a consistent reading. I tied the input of adc to ground and still the lsb blinks. Is there any way to correct it? Or how can i write the vhdl code (...)
I need vhdl code for a to d converter ic ads1271, for my project, istudied data sheet of ads1271, but i fail understood operational process
Hello. I'm a beginner in vhdl and want to interface adc(ADS7800) with FPGA virtex-5 can anyone help me in this.? regards.
Hi, I need vhdl code for interfacing on board 8 bit (0808) adc-DAC to FPGA SPARTAN 2 pl. help me
Yes the problem in using library numeric and unsigned. u removed numeric and use only unsigned library. and your code having a real function. so ur having a another problem in real. real function cannot be synthesize in ISE. at that same time real synthesized inside of function in vhdl package declaration.
hello, i need a vhdl code for fifo memory to store binary values from a high speed 8 bit resolution adc. can help me give the code and the ucf file for implementing it on spartan 6 sp605( fpga kit).?? thank you you can automatically generate it with xilinx core generator (coregen) you (...)
hello, can any one suggest me with a simplified vhdl code for interfacing spartan 6(sp605) with an ic adc 0804? adc 0804 data sheet. spa605 thank you. all you
Hey All! I need to write vhdl code for ADS8558. Its a 16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL so far I am unable to figure out how should I do it. I have Xilinix ISE 10.1 and the board I am using is Virtex2PRo.
I am doing project on BPSK Modulation and demodulation implementation on FPGA Spartan 3E. if you help us it will grateful, we need vhdl code adc/DAC interface with Spartan 3E. Regards & thanks Abhinav
I have found this code on search.
i am in need of simple adc code in vhdl with analog input at port grater the bit better it will be can anybody help me ?
Please help me regarding vhdl code to interface adc0804( the 8-bit adc) to FPGA . please send the vhdl code as early as possible. I am waiting for ur reply. pls its urgent. with regards Nagaraj
Hi, I need vhdl code for interfacing on board 8 bit adc-DAC to FPGA SPARTAN 2 pl. help me
I cannot get the following code to produce the correct results of a subtraction and I'm not sure what is wrong with it. Current is an input from an adc that is in two's complement form. The clk is the same for both the adc so that I should be clocking in a new sample at the same rate of the (...)
hi guys in one part of my project i'm dealing with high speed adc ( ADS1274 from ti) . i need to vhdl spi driver for that, any suggestion? the datasheet is here : i know that the spi drivers depends on functionality and properties of relevant device, i'm wondering if u have any suggest
can someone pls provide me with the vhdl code to interface adc0804 (8 bit parallel adc) with Cyclone II DE1 FPGA? this is urgent pls:cry:
could anyone help me with the code of interfacing the adc in spartan 3a kit. vhdl will be better. any other info will also be helpful thanks 4 ur replies
Hey,everybody. I am constructing an vhdl code for clock divider and specification of 2 pins. I need to trigger 2 pins using DE2 board for 1 clock cycle(auto trigger down itself after 1 clock cycle). However, i have no idea how to convert that output of my clock divider for the clock of my pin (...)
hi, i want to interface adc with a cpld ,how can i do the same
I have constructed the vhdl code for master(FPGA) and slave (adc). What are you trying to achieve? If you want to control the adc, you have to design a SPI master interface. A vhdl code for the slave would be needed only to simulate the slave's behaviour. (...)
Hi, i am a beginner in designing using vhdl. I need to construct interconnection between adc(ADS7861 from Texas) and FPGA DE2 board. I have been told to use a SPI --- a serial to parallel SPi interface between adc and FPGA. I have constructed the vhdl code for master(FPGA) and slave (...)
Hi guys, I am designing a circuit that will convert 12V signal into digital through a Comparator and that needs to be read by FPGA. (1) If I don't use a common GND for the comparator and the FPGA, do I have to use Differantial inputs? (2) Which IO Standard do I use, and where can I get their specifications (3) Can someone advise me o
I want vhdl code for interfacing adc (SP774BT) to FPGA>>> I have attached my datasheet
hi, im working on a project in vhdl where an FPGA takes readings from a temp and pressure senror, when the readings reach a preset level then they should turn on a DC motor pump and then switch it back off when the reading go back below the treshold. I am not experienced in this and need help, any code examples or links could help me in my studi
Hi, i am new to vhdl. I am provided with a spartan3 fpga. After sourcing for an adc(10 bit), i have selected the microchip (MCP3002) which requires SPI. I am a bit confused on how to start. I've tried reading vhdl code but it doesnt make sense to me. On the adc datasheets, i know that i (...)
hi, There is a version of vhdl called vhdl AMS. It can be used for mixed signal design. Therefore adc can easily modeled by using vhdl AMS.
hi friends,, i need code vhdl code or verilog code for adc ans DAC please help me .. with thanks raj..
Hi! I'm a bit new to fpga-s. I need help or sample code (vhdl if possible) for the A/D module. I need a controller that initiates conversion and stores the data in a register or variable. If you can, please help! Thanx!
can anyone send a code(vhdl) for adc..pls
use fdatool in matlab to design ur filter quantize it to the required data format and generate a verilog/vhdl code + test bench. it would be really simpler to verify. regards srinivas The decimation filter is a multistage filter. Because I design each stage separately. How the testbench of the decimation filter be
dear friends, I'm learning vhdl .i want an example of vhdl code for connecting a flash adc to the FPGA. thanks a lot
finally i get the waveform !!!! anyone here can guide me for the next progress that is how to get the waveform for adc using visual elite??? any component can replace it?? example 8 bit counter?? need someone to guide me... oh ya... today i was try to get the octal latch waveform and the (...)
Can I use certian VHL attribute to direct the synthesizer to assign certain Input or output pin to certain pin location on the target FPGA ?