61 Threads found on edaboard.com: Vhdl Code Spi
i need code vhdl code or verilog code for ADC ans DAC please help me ..
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.09.2007 01:26 :: rajakash :: Replies: 3 :: Views: 3274
Hi, i am new to vhdl. I am provided with a spartan3 fpga. After sourcing for an ADC(10 bit), i have selected the microchip (MCP3002) which requires spi.
I am a bit confused on how to start. I've tried reading vhdl code but it doesnt make sense to me. On the ADC datasheets, i know that i need SCK,CS,Din,Dout. What (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.09.2008 08:54 :: ombadei :: Replies: 0 :: Views: 1543
I want to feed 4 signals to a MUX (run on FPGA supplied clock), and then to a comparator, which feeds the 4 bits in series to an FPGA input. Will this work?
Can anyone advise me on how to go about making verilog or vhdl code for reading serial data - either spi or otherwise.
Also, i need advice on synchronization (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.05.2009 05:29 :: roddyalan :: Replies: 0 :: Views: 863
PLEASE SEND ME,spi vhdl code ,READ DATA FROM spi AND WRITE TO INSIDE MEMORY OF FPGA IC XILINX SPARTAN 2
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.09.2009 01:37 :: bnmbnm :: Replies: 1 :: Views: 1896
Do you need a vhdl code for implementation on a FPGA?
EDA Jobs :: 09.01.2012 03:25 :: Zerox100 :: Replies: 1 :: Views: 762
I am doing project on BPSK Modulation and demodulation implementation on FPGA Spartan 3E.
if you help us it will grateful, we need vhdl code ADC/DAC interface with Spartan 3E.
Regards & thanks
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.02.2012 05:48 :: Abhi_7 :: Replies: 2 :: Views: 2627
How about reading a vhdl tutorial? or a good vhdl textbook. Ashenden's book is supposed to be good:
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.05.2012 04:48 :: TrickyDicky :: Replies: 2 :: Views: 1228
Hi every one
I have implemented spi receiver which has communication with Atmega128 spi. every thing is fine but some times I have some problem like data shift of one or two bit!!! I don`t why. I attach my code here, so if some one can help to find out what is the problem with my code ( I am not professional and I am new (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.08.2012 02:48 :: arash rezaee :: Replies: 8 :: Views: 652
mates..this is what iam crying for last 6 months..
systemgenerator will give vhdl code as well as testbench codes for matlab scripts specific for dsp related apps,,
can anyone provide a full version of system generator
PC Programming and Interfacing :: 15.07.2002 09:52 :: synq :: Replies: 32 :: Views: 14950
There Are Lots Of spi Deratives. The Best Thing To Do, Is To Examine The Datasheets Of The Device You Are Interfacing, For The Required spi Format.
vhdl Is Not C, So You Should Always Write Your Own code.
spi Is Very Simple - There Is Master And Slaves, So No Arbitration Is Needed,
Also There Is One (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.09.2005 07:48 :: shawndaking :: Replies: 29 :: Views: 50491
Hi, im a studnet who needes to create a routine/routines that take readings from 2 spi bus sensors (pressure & temp) and the microblaze must take these readings and when the values of they're inputs reach a certain level/treshold the spartan board must activate a 12volt dc pump to spray water for a set period of time....then repeat the process.
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.11.2008 11:32 :: sht11help :: Replies: 5 :: Views: 915
Hi, i am a beginner in designing using vhdl. I need to construct interconnection between ADC(ADS7861 from Texas) and FPGA DE2 board. I have been told to use a spi --- a serial to parallel spi interface between ADC and FPGA. I have constructed the vhdl code for master(FPGA) and slave (ADC).
I understand (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.12.2009 11:40 :: LF_LF :: Replies: 0 :: Views: 680
I am not sure but this might assist you.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.07.2010 11:40 :: hakeen :: Replies: 4 :: Views: 1782
first... are you trying to send from FPGA to DAC?, because in your post I can't see what are you trying to do.
you should create a vhdl spi bus controller to send the data to the DAC, search for similar topics in this forum and you will find help.
in that program you have to send to values to the DAC, the max and the min.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.07.2010 01:11 :: mersault :: Replies: 3 :: Views: 854
hello all, i have with me a spartan 3 starter board that has 4 LEDs and 4 capacitive touch pads that can be interfaced with. i have an upcoming project that would use the spartan 3A FPGA and i figured this starter board would be a good place for me to start as i have no experience with FPGAs and vhdl programming.
i intended to program the FPGA
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.04.2011 23:52 :: ptjw :: Replies: 12 :: Views: 2907
I'm using Spartan 6,SP605.I would like to request for verilog/vhdl code for implementation of FPGA and Synchronous Serial Interface.Thank you.
Hi, Please clarify your query. If you are looking for source code for how the FPGA itself is designed and taped out, Its proprerty of Xilinx and I am afraid you will not get tha
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.07.2011 04:42 :: Iamventure :: Replies: 3 :: Views: 487
i tested and doesn't work.....
Error listed from the quartus
The problem isn't related to Verilog or vhdl coding. You need to check the pins assignments. The archived project compiles in Quartus V11 as is, so you apparently have applied changes to it.
It's the DE0_NANO_GSensor example from the DE0_Nano_v1.0.5_SystemCD, translat
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.02.2012 02:29 :: FvM :: Replies: 17 :: Views: 2574
I am in urgent need of a test bench.
I have the verilog version of it. It would be of great help if anyone converts it into vhdl.
* TESTBENCH FOR spi TO I2C
* January 2007
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.03.2012 11:21 :: shhrikant1 :: Replies: 1 :: Views: 687
i have been working on vhdl code for my spi controller. consisting of a master and slave for data transfer.
this is my code
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.02.2013 17:58 :: deric24 :: Replies: 1 :: Views: 222
I am new user of this site & I want vhdl cod for serial communication,so plz send me that.
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.06.2013 01:40 :: girishmahamuni :: Replies: 2 :: Views: 436
Hi to all. any body can help me for programming synthesizer si4136 with vhdl code?
I need for my final project.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.08.2013 10:33 :: firstname.lastname@example.org :: Replies: 12 :: Views: 469
Does anyone have Verilog/vhdl source code for a synchronous serial port that interfaces to DSP's or A2D's ?? Can you share ??
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.12.2004 01:28 :: dspcode :: Replies: 1 :: Views: 1943
I'm writing a simple spi master interface in vhdl for a Coolrunner II CPLD. The clock rate is no higher than 20MHz. The data on MOSI line needs to appear a few ns before the rising edge of the clock, in order for the slave to catch the data.. But since the SCK line and the clock feeding the shift register are the same, the data will appear sim
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.02.2005 07:04 :: Mercury :: Replies: 8 :: Views: 1569
need help with spi3....i want to implement in vhdl......any gud material for reference or any docs or code is most welcome....
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.02.2005 09:13 :: chaitu2k :: Replies: 0 :: Views: 770
I need to implement sysstem packet interface 3 .....i was wondering if i could get any SM's or a vhdl or verilog code or any design documents etc in regards to it....
ASIC Design Methodologies and Tools (Digital) :: 15.02.2005 23:51 :: chaitu2k :: Replies: 2 :: Views: 996
currrently i'm handling an fpga APEX20K board and just getting use to i'm suppose to implement an spi interface using the nios processor and the avalon switch this point of time, i'm only familiar with vhdl and i was wondering if any1 has the source code in vhdl for a spi interface.
i'm going (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.09.2005 15:26 :: E_D_W_I_N_83 :: Replies: 3 :: Views: 1996
I have a rather simple question. Is there a vhdl code for the Microprocessor - FPGA interface.
I am writing data from a microprocessor to FPGA (into BRAM). I need a generic code for a interface between microprocessor and FPGA BRAM. I will be using Altera FPGA.
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.05.2006 07:48 :: bismillah :: Replies: 5 :: Views: 1391
Hi frendz i have recvd a task. Plz help me how shall I approach the problem.. its spi in vhdl
Write a vhdl program that implements a spi interface to a CPU, the received bytes are passed to a command parser for decoding.
serial protocol in the spi should be as follows:
1- /CS goes (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.09.2006 03:09 :: anniemanuja :: Replies: 7 :: Views: 8977
I need to read data from flash (m25p10A-ST) to fpga,
is anyone know if exist vhdl code for this somewhere?
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.10.2006 03:20 :: nio123 :: Replies: 7 :: Views: 1039
Hi frendz I need to design an Ultrasonic range finder.
Plz help as i am an amateur wid vhdl. I am uploading the diagram and for more information plz ask me. Also it doesnt have to be very
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.11.2006 03:04 :: greprac :: Replies: 6 :: Views: 1533
Verilog and vhdl models of and ATMEL spi FLASH can be found here:
They should be compatible with WinBond parts (unless you want to use quad mode, etc)
ASIC Design Methodologies and Tools (Digital) :: 06.08.2010 19:34 :: jbeniston :: Replies: 7 :: Views: 4769
hi i m new in fpga and vhdl programming. if any body have code for ramp generation in vhdl please pest it.and also suggest that how to define fpga pin to send this program in spi unit in fpga board for converting digital input to ramp output.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.12.2009 21:58 :: vishnu shankar :: Replies: 2 :: Views: 1780
I have constructed the vhdl code for master(FPGA) and slave (ADC).
What are you trying to achieve? If you want to control the ADC, you have to design a spi master interface. A vhdl code for the slave would be needed only to simulate the slave's behaviour.
For the code, i found out some (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.12.2009 08:17 :: FvM :: Replies: 10 :: Views: 2068
I need someone who can do for me:
• behavioral model of controller for 8-Mb Flash memory M45PE80
• serial spi communication
• write and erase simulation of any memory cell
• memory contents stored in a text file
I need some vhdl project with test bench.
More info about M45PE80: www.fre
EDA Jobs :: 18.12.2009 13:06 :: ksynon :: Replies: 1 :: Views: 615
i am doing a project 'hardware implementation of DPLL using vhdl'. We are using the IC ADF4156 as the phase detector. the inputs to the registers are given as serial inputs from FPGA. we hav five registers in ADF4156 and we hav got a set of values to input the registers . hw can we do this by spi interfacing? or can i do this in any other way?[/quo
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.01.2010 13:06 :: aravind326 :: Replies: 1 :: Views: 792
I want to use the ADC on spartan 3e kit. I think I need to use spi interface to connect the ADC to the FPGA. I wonder if I can find a vhdl source code for using ADC with spi interface. Please help me...
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.04.2010 08:54 :: ytmm :: Replies: 6 :: Views: 3505
in one part of my project i'm dealing with high speed ADC ( ADS1274 from ti) . i need to vhdl spi driver for that, any suggestion?
the datasheet is here :
i know that the spi drivers depends on functionality and properties of relevant device, i'm wondering if u have any suggest
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.05.2010 13:18 :: ifathirad :: Replies: 0 :: Views: 1694
They have two vhdl implementations for spi. The first is OPB to spi and the second is spi flash controller.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.06.2010 15:02 :: amraldo :: Replies: 2 :: Views: 1204
Connect all the digital signals on the DAC to the FPGA and the write an FPGA controller to send the data based on the timing of the DAC and you will see the proper signal coming out.
The issue with the AD9706 is that you need to change the setting of the DAC via spi, you can do that either by adding a spi controller to your FPGA and let the Core
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.06.2010 07:03 :: farhada :: Replies: 3 :: Views: 1897
also, I do like the "vhdl-THESIS/project_verilog" part of the project path.
Was thinking the same thing. :)
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.03.2011 08:41 :: mrflibble :: Replies: 3 :: Views: 1630
i am to configure a spartan 3A to interface with a SD card reader in spi mode using MOSI, MISO, CS and CLK.
i have written code in vhdl to implement this, but cannot verify whether it works until the actual hardware is here (which is still a few weeks away).
i currently have a few simple questions:
lets say i have a (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.05.2011 23:06 :: ptjw :: Replies: 3 :: Views: 1375
For the spi master code ... I'd suggest using the search function on this forum for a bit. spi (and verilog/vhdl implementations) pop up often enough.
As for what pins on the board, I'd guess the DE board documentation shows you which pins. Plus, generally for boards like that the manufacturer has some constraints files (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.07.2011 21:04 :: mrflibble :: Replies: 1 :: Views: 1454
this problem nearly drive me crazy....
the FPGA works as a spi-slave, and a MCU works as master. spi speed is 500KHz. The communication was set up but only 60% message was received correct in master side.
The data on MISO is not stable, sometimes lost several bits......the codes are;
TP276 <= sigspiRx; (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.01.2012 12:07 :: friday182 :: Replies: 1 :: Views: 818
I have been able to initialize and write to an SD card in spi mode, but when I am trying to use the same vhdl code to write to a 32 GB SDHC card it doesn't work. My initialization is as follows:
1) CMD0 , CS = 0
then I start reading or writing. What is different when it is an SDHC card. Also in (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.02.2012 09:13 :: am85 :: Replies: 0 :: Views: 626
My experience with Altera reference designs is, that they are basically working. But you may want to change some features here or there and then you get the chance to introduce design errors that need to be debugged.
I didn't check it the code. Verilog testbench issues are mostly related to not knowing which libraries have to be included. It's s
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.03.2012 12:15 :: FvM :: Replies: 9 :: Views: 1053
I am trying to configure an ADC using an FPGA. I can read the default values from the ADC register properly, but I'm unable to write to those registers.
The fpga clock is 48 MHz and serial clock for the ADC is 8 MHz. The vhdl code that I've written is given below.
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.04.2012 22:25 :: aroy :: Replies: 4 :: Views: 472
Any one did interface onboard flash memory of Digilent Atlys board ? Please share vhdl /Verilog code for reading data from onboard spi flash memory of Digilent Atlys board.
In which mode the flash is configured ? like, Quad output fast read, Quad input/output fast read, Quad command fast read, etc......
Please help me. I (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.05.2012 13:06 :: sajkumar :: Replies: 0 :: Views: 850
First suggestion, please append your post to the thread where it belongs to.
Secondly, there's a disambiguation problem with your post. "spi-4.2" addressed by Xilinx is a high speed (Gigabit per second) interface, that has nothing to do with the spi interface standard used by a DSP processor.
A basic spi interface is just a few lines (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.05.2012 11:51 :: FvM :: Replies: 1 :: Views: 353
I am implementing spi bus protocol in vhdl, the data should be transmitted during +ve rising edge of clock
i have written this code but i am unable to get the desired result, am i implementing the right way or no???? any help is appreciated:
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.06.2012 08:02 :: VishwanathAmbli :: Replies: 7 :: Views: 989
Hi, I'm experiencing a strange problem with my project. I'm using the Nexys 3 board from digilent (spartan 6).
I have a lot of components in my project (RAM access, UART communication, spi communication, etc.). Until yesterday, every part of my code was functionning fine on the Nexys 3 devellopment kit. But now, when I'm adding or just changing a
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.07.2012 11:32 :: tmor :: Replies: 1 :: Views: 434