96 Threads found on edaboard.com: Vhdl Full Adder
if you use a programmable logic and you use vhdl or verilog you must define a vector of 9 bits.
when you add you 3 8 bits you have the carry gratis.
Professional Hardware and Electronics Design :: 18.02.2003 22:46 :: firstname.lastname@example.org :: Replies: 1 :: Views: 1580
Here's vhdl code for a full adder and Half adder:
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.12.2003 20:30 :: Jayson :: Replies: 3 :: Views: 2199
sum <= a xor b xor carry_in; -- each is 1 bit
carry_out <= (a AND b) OR (a AND carry_in) OR (b AND carry_in); -- either 2 of the input is 1 then there is a carry out
we need bout 7 basic logic gates... how many gates required to build the decoder? is it cost effective?
i wonder is it better way to use decoder as multiplier so no
Electronic Elementary Questions :: 27.09.2005 10:27 :: sp :: Replies: 14 :: Views: 18370
I am having a Halfadder Module... I want to make a full adder by using the Halfadder module... How to implemnt it in vhdl?....
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.01.2006 15:41 :: kumar_eee :: Replies: 3 :: Views: 4247
Hi Werner ;-)
for a vhdl solution s. Similar Threads below. For schematics use G00GLE, s. this thread.
Analog IC Design and Layout :: 27.03.2012 19:34 :: erikl :: Replies: 7 :: Views: 1838
you can use the common "+" statement to indicate it is a plus operation, and use according synopsys directive statement in your vhdl comment, then DC will call the DesignWare library cell to do it
ASIC Design Methodologies and Tools (Digital) :: 13.06.2006 11:40 :: xuanzhu :: Replies: 3 :: Views: 629
I need a help in writing a vhdl cobe for a 4bit full-adder
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.10.2006 22:33 :: fm_com_28 :: Replies: 1 :: Views: 32688
Refer book to understand design and test bench writing :
Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using vhdl or Verilog
by Douglas J. Smith
Also below link is useful
ASIC Design Methodologies and Tools (Digital) :: 21.11.2007 11:24 :: barkha :: Replies: 7 :: Views: 1962
Hii I am having a problem with a test bench in vhdl
the following is my code for a full adder::
entity adderwa is
port(a,b:in std_logic_vector(n-1 downto 0);
sum:out std_logic_vector(n-1 downto (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.10.2008 01:44 :: prashant_sharma :: Replies: 1 :: Views: 4336
i have just learned to write on vhdl and I have completed my first full adder code using components for the xor, and, or gates but im not sure if its right, could someone please tell me if this is right? I do not have vhdl ive written this on notepad..
-- For XOR gates:
use IEEE.std_logic_1164.all; (...)
ASIC Design Methodologies and Tools (Digital) :: 08.11.2009 05:57 :: OKcomputer6 :: Replies: 0 :: Views: 542
can anybody give the idea for desining a 1-bit full adder of behavioral modeelling using case/if ststements
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.01.2010 14:20 :: mohan_ece :: Replies: 1 :: Views: 5708
Hello every one
i need your help in vhdl .
actually i need a code to design a full adder using a Decoder ..
and thank you for such great forum ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.04.2010 22:01 :: Student89 :: Replies: 1 :: Views: 815
You can download the Xilinx Webpack for free here: Xilinx: Downloads
A fulladder vhdl code looks like this:
-- This is just to make a reference to some common things needed.
-- We declare the 1-bit adder with the inputs and outputs
-- shown in
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.09.2010 08:50 :: mindthomas :: Replies: 12 :: Views: 5360
I need a help in writing a vhdl cobe for a 2bit full-adder using 2 half adder
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.10.2010 23:03 :: fooofaaa :: Replies: 2 :: Views: 4761
Just write vhdl code based on truth table.
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.11.2010 04:28 :: lostinxlation :: Replies: 3 :: Views: 1336
first design four bit adder from one bit adder .then you can design 16bit adder from 4 full adder circuit.the code is available for this module in Xilinx website.
Thanks a lot for your reply! The 4 bit adder is a pure combinational circuit. It seems that the (...)
ASIC Design Methodologies and Tools (Digital) :: 20.12.2011 16:53 :: liusupeng :: Replies: 11 :: Views: 1435
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.05.2012 21:08 :: permute :: Replies: 1 :: Views: 843
I have to develop a program on leakage current estimation and reduction in a full adder circuit using vhdl. Please Reply ASAP. Thanks.
Software Problems, Hints and Reviews :: 23.11.2012 08:54 :: yatin009 :: Replies: 0 :: Views: 157
vhdl language is the same for both of them.
1) Perhaps the question should be which constructions are supported by the synthesis tool I use, which can limit my coding style. Or...
2)do I prefer very behavioral coding versus low level structural coding: in first case code can be portable but, in last case, if you make calls to library components
ASIC Design Methodologies and Tools (Digital) :: 15.04.2004 23:34 :: fivaro1 :: Replies: 14 :: Views: 2014
u look into this book
The Designer's Guide to vhdl
by Peter J. Ashenden,
u got lot of exercise that will make to think,
it has got some interesting exercises u can make use of it and enhance ur design skills in vhdl,
there are also some university websites which offer course in vhdl,
they have also posted some (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.08.2005 06:32 :: au_sun :: Replies: 5 :: Views: 1522
use your loaf use google
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.10.2005 03:12 :: VSMVDD :: Replies: 2 :: Views: 1489
can you tell me something about designing a up down counter using only half adders (and flip flops) say for 4 bit ?
vhdl code would also do ...or a logic diagram or a link....?
ASIC Design Methodologies and Tools (Digital) :: 02.12.2005 05:57 :: truebs :: Replies: 4 :: Views: 2257
Do you mean 16-bit BCD adder???
If yes see the link below...
Its in verilog you can convert it into vhdl ..
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.12.2006 06:48 :: nand_gates :: Replies: 6 :: Views: 1600
could you give some details about this adder because we need it for vhdl design....
Microcontrollers :: 13.12.2006 06:36 :: zhaorah :: Replies: 0 :: Views: 917
Is this a student educational project? Are you required to use old 74xx parts? That's a lot of wiring, and the logic won't run very fast.
Instead, how about designing the logic in Verilog or vhdl, and then implement it in an FPGA? You can buy a nice little FPGA development kit for about $100 to $150 US.
Embedded Systems and Real-Time OS :: 05.04.2007 01:40 :: echo47 :: Replies: 5 :: Views: 1670
I NEED adder vhdl CODE
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.08.2007 15:13 :: sumant.thapliyal :: Replies: 7 :: Views: 34950
i am trying to implement/ the pipeline and parallel in vhdl for the given file
for that i am choose the a ckt which is shown in file (without pipeline& parallel )
after complete analysis of this ckt i will go for pipeline & parallel .
i would like to ask suggestion about adder , what type of adder should i ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.12.2007 05:34 :: manish12 :: Replies: 1 :: Views: 781
4x4 multiplier can be implemented with a scaling accumulator multiplier which performs multiplication using an iterative shift-add operations.
EDIT: check this pdf which contains 4x4 multiplier
ASIC Design Methodologies and Tools (Digital) :: 28.04.2009 08:57 :: ray123 :: Replies: 4 :: Views: 2450
I take this error after simulating this code: can't find a pinstub/port in the symbol, function prototype, or other construct 'test' that represents a design file that corresponds to pin XA2 in the file.
this is a 16 bit CSA simulator
Thank you for help
The code is Below :
--16 BIT CARRY SKIP adder----
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.06.2009 11:51 :: minemercan :: Replies: 0 :: Views: 551
Hi I am trying to teach myself vhdl and I just started going through a book and came across a first example to try. The example is a full adder and I have the code finished and compiled with no errors I just cannot figure out how to simulate it (particularly I do not know how to set a,b,c_in with input signals). I am using ModelsimPE and (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.01.2011 22:37 :: Nightlamp :: Replies: 3 :: Views: 529
Had just a quick question about a vhdl testbench I made. I am testing a full adder (a,b,c_in are my inputs) and wanted to simply test from (0,0,0 to 1,1,1) as to get all possible combinations of inputs. The reason for this project is just a simple start at vhdl/coding in general.
Anyway my question is this I have this (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.01.2011 00:00 :: Nightlamp :: Replies: 5 :: Views: 1015
I am doing Tiny Encryption Algorithm (TEA) research work using vhdl language. I have to come up with a 1 bit and 8 bit full adder(FA) & subtractor and 8 bit XOR. I have to encrypt and decrypt them and use shift left 2 times, and shift right 3 times. Block sizes are 16 bits, Key sizes are 32 bits and cycles 8 bits. Delta is given by (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.04.2011 12:08 :: mohdsalim :: Replies: 1 :: Views: 1174
Hi to all,
i'm studying the vhdl language, and i'm trying to do some exercise!
i did a simple full adder, it works, i have already test it, and with the same criteria i did a ripple carry adder at 8 bits,but i have a problem with the simulation, the error is:
# Loading work.rcatb(tb)
# ** Warning: (vsim-3473) Component (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.04.2011 19:48 :: tj.diego :: Replies: 2 :: Views: 690
Sorry, is it possible to explain from the top onwards?
I think, reading a vhdl text book may be more effective.
To understand the code's functionality, I would refer to this equivalent form:
if reset = '1' then
c <= (others => '0');
elsif clk'event and (clk = '1') then
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.05.2011 08:11 :: FvM :: Replies: 19 :: Views: 1236
I'm writing a vhdl code for Xilinx Spartan 3e with Xilinx ISE software and simulating with ISE simulator. The code's function is to convert digital to analog by using the SPI interface. So far I've managed to get an analog square wave but I want something more fun than a square wave. The square wave follows a divided clock "co". The SPI gets 32 bit
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.10.2011 08:58 :: etoochy :: Replies: 25 :: Views: 567
I am having a problem with my vhdl code made for a multiplication of binary numbers. It keeps showing errors that i do not understand. Is there anyone that could give me a hand, so i upload the program?
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.11.2011 14:37 :: Antros48 :: Replies: 19 :: Views: 1108
You are welcome to see some free projects and vhdl tips at:
vhdl, verilog, design, verification, scripts, ...
Record array in vhdl using free simulator GHDL. record tip
A simple guide describing how to print from vhdl code. print tip
The importance of stop on fata
Embedded Systems and Real-Time OS :: 07.12.2011 13:06 :: pini_1 :: Replies: 3 :: Views: 665
can anybody help me with a vhdl code. i trying to write a code for a carry skip adder. i dont know how to use index to implement the block for n bit. i can do it for like 20 bit but not for n bit.
for example p(0)= a(0) or b(0); for 1st fulladder in the block. the block consist of 5 (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.03.2012 16:22 :: majerio :: Replies: 19 :: Views: 1819
Old vhdl versions had the problem that a port of the buffer type must be continued as buffer through the hierarchy. The restriction doesn't apply to recent vhdl. But the suggestion to copy the signal is reasonable for clarity, though.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.06.2012 10:11 :: FvM :: Replies: 6 :: Views: 605
I was asked today in an interview this question, Why do we need to have the same operand sizes for addition in vhdl, while in multiplication we don't? however we expect that both the result of addition and multiplication be of a bigger size than the operands!
Meaning that if a is std_logic_vector(3 downto 0) and b is std_logic_vecto
ASIC Design Methodologies and Tools (Digital) :: 30.07.2012 01:16 :: AhmedIbrahim :: Replies: 6 :: Views: 1594
I'm assuming that the '0' & X calls a function "&"(A,B : std_logic_vector) that returns a vector (0 to len(A)+len(B)-1).
Yes, vhdl defined the default direction as "to". This is actually common outside of hardware design. Of course HW designers tend to favor MSB on the left.
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.10.2012 05:43 :: permute :: Replies: 7 :: Views: 235
i'm working on it! ,,,
Ok ,,,, I appears that those files were crated with Open foundation and they are in schematic form .I tried to create a new project unde ISE 6.2 and is able to add the files to a project ,.But it won't read that old format
By usign E-estudio i was able to convert the Edif 2.0 into vhdl code .
But the thing is that the
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.09.2004 20:56 :: eltonjohn :: Replies: 44 :: Views: 20065
Think may be useful, evita vhdl and verilog links from
ASIC Design Methodologies and Tools (Digital) :: 20.01.2003 01:22 :: elnenez :: Replies: 11 :: Views: 3898
your can design it at gate level. i.e. use the "or" logic\"xor"logic\"and" logic. I completed one 64-bits signed adder last month using the verilog. I think it's easy to transfer it into vhdl code if you like to.
ps you can not find the existing one on the internet. so read the article carefully and depend on yourself.
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.10.2004 05:07 :: craftfox :: Replies: 4 :: Views: 1502
is there anythin specific.. actually there are lotsa things u can implement. wot did u get with the xilinx's developer's kit.. did u get a general purpose kit? if u had purchased a general purpose kit u can try some programs like half, full adder and subtractor, u can also try the MUX and Demux programs..
which version of xilinx webpack did u ge
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.12.2004 01:53 :: arunragavan :: Replies: 4 :: Views: 1135
It?s nice to see you here.
1. That?s right. For sequential circuits you need a register too. Registers are part of LE (Logic Elements, Altera) / CLB (configurable logic block, Xilinx).
2. A LUT with 4 inputs and one output has a depth of 16. For each value of the inputs you get a corresponding output. So the inputs are working li
Electronic Elementary Questions :: 19.05.2005 17:07 :: cube007 :: Replies: 7 :: Views: 719
I am not good with mathematical implementations, but if you send me your vhdl code for this section of the your algorithem, I can give you some feedback. Also, give me some information about the type of device you are targetting, the clock speed, and any other constrains you have. You can send it to my home e-mail at ny_farhad@
Digital Signal Processing :: 29.05.2005 14:28 :: farhada :: Replies: 6 :: Views: 696
To speak simply, verification is like to run simulation to verify that the function of your design is correct. So we normal call it functional verification to diff is from validation which normally use fpga to verification design.
Actually it is a complicated and time consuming process in the ASIC design flow.
If you spent about %30 on coding, t
ASIC Design Methodologies and Tools (Digital) :: 29.07.2005 11:38 :: brianhe :: Replies: 10 :: Views: 1046
I am just curious how to implement algorithm into hardware. Let say, I have written a convolutional in C++ language for simulation purpose. Then, what should I do to implement in hardware?Is it using FPGA or vhdl?Any good informations about it? Thanks.
Digital communication :: 07.05.2006 23:32 :: cwjcwjcwj :: Replies: 7 :: Views: 1014
I've some interview questions about digital circuit, vhdl and ASIC/FPGA. I think it's a good opportunity for us to discuss these questions. Maybe it's very helpful when we want to seek for jobs in the near future. The following is the first quesion.
Interview question #1:
What are the different adder circuits you studied?
Here is m
ASIC Design Methodologies and Tools (Digital) :: 10.12.2006 07:20 :: richardyue :: Replies: 11 :: Views: 1546