48 Threads found on edaboard.com: Vhdl Full Adder
if you use a programmable logic and you use vhdl or verilog you must define a vector of 9 bits.
when you add you 3 8 bits you have the carry gratis.
Professional Hardware and Electronics Design :: 18.02.2003 16:46 :: email@example.com :: Replies: 1 :: Views: 1875
Here's vhdl code for a full adder and Half adder:
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.12.2003 14:30 :: Jayson :: Replies: 3 :: Views: 2545
I am having a Halfadder Module... I want to make a full adder by using the Halfadder module... How to implemnt it in vhdl?....
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.01.2006 09:41 :: kumar_eee :: Replies: 3 :: Views: 7925
Hi Werner ;-)
for a vhdl solution s. Similar Threads below. For schematics use G00GLE, s. this thread.
Analog IC Design and Layout :: 27.03.2012 13:34 :: erikl :: Replies: 7 :: Views: 2237
you can use the common "+" statement to indicate it is a plus operation, and use according synopsys directive statement in your vhdl comment, then DC will call the DesignWare library cell to do it
ASIC Design Methodologies and Tools (Digital) :: 13.06.2006 05:40 :: xuanzhu :: Replies: 3 :: Views: 746
I need a help in writing a vhdl cobe for a 4bit full-adder
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.10.2006 16:33 :: fm_com_28 :: Replies: 5 :: Views: 42305
Hii I am having a problem with a test bench in vhdl
the following is my code for a full adder::
entity adderwa is
port(a,b:in std_logic_vector(n-1 downto 0);
sum:out std_logic_vector(n-1 downto (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.10.2008 19:44 :: prashant_sharma :: Replies: 1 :: Views: 5069
i have just learned to write on vhdl and I have completed my first full adder code using components for the xor, and, or gates but im not sure if its right, could someone please tell me if this is right? I do not have vhdl ive written this on notepad..
-- For XOR gates:
use IEEE.std_logic_1164.all; (...)
ASIC Design Methodologies and Tools (Digital) :: 07.11.2009 23:57 :: OKcomputer6 :: Replies: 0 :: Views: 642
can anybody give the idea for desining a 1-bit full adder of behavioral modeelling using case/if ststements
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.01.2010 08:20 :: mohan_ece :: Replies: 1 :: Views: 6225
Hello every one
i need your help in vhdl .
actually i need a code to design a full adder using a Decoder ..
and thank you for such great forum ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.04.2010 16:01 :: Student89 :: Replies: 1 :: Views: 1009
I need a help in writing a vhdl cobe for a 2bit full-adder using 2 half adder
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.10.2010 17:03 :: fooofaaa :: Replies: 2 :: Views: 5356
howa can i design a full adder ( vhdl) using structural mode and using gates not 2 half adder and 1 or gate
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.11.2010 16:40 :: sara0 :: Replies: 3 :: Views: 1494
first design four bit adder from one bit adder .then you can design 16bit adder from 4 full adder circuit.the code is available for this module in Xilinx website.
Thanks a lot for your reply! The 4 bit adder is a pure combinational circuit. It seems that the (...)
ASIC Design Methodologies and Tools (Digital) :: 20.12.2011 10:53 :: liusupeng :: Replies: 11 :: Views: 2930
Create a vhdl file fa.vhd to implement a structural model of a 1-*‐bit full adder.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.05.2012 13:45 :: spider_man :: Replies: 1 :: Views: 1063
I have to develop a program on leakage current estimation and reduction in a full adder circuit using vhdl. Please Reply ASAP. Thanks.
Software Problems, Hints and Reviews :: 23.11.2012 02:54 :: yatin009 :: Replies: 0 :: Views: 299
sum <= a xor b xor carry_in; -- each is 1 bit
carry_out <= (a AND b) OR (a AND carry_in) OR (b AND carry_in); -- either 2 of the input is 1 then there is a carry out
we need bout 7 basic logic gates... how many gates required to build the decoder? is it cost effective?
i wonder is it better way to use decoder as multiplier so no
Electronic Elementary Questions :: 27.09.2005 04:27 :: sp :: Replies: 14 :: Views: 21791
use your loaf use google
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.10.2005 22:12 :: VSMVDD :: Replies: 2 :: Views: 1781
can you tell me something about designing a up down counter using only half adders (and flip flops) say for 4 bit ?
vhdl code would also do ...or a logic diagram or a link....?
ASIC Design Methodologies and Tools (Digital) :: 01.12.2005 23:57 :: truebs :: Replies: 4 :: Views: 3120
Do you mean 16-bit BCD adder???
If yes see the link below...
Its in verilog you can convert it into vhdl ..
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.12.2006 00:48 :: nand_gates :: Replies: 6 :: Views: 2305
could you give some details about this adder because we need it for vhdl design....
Microcontrollers :: 13.12.2006 00:36 :: zhaorah :: Replies: 0 :: Views: 1202
Refer book to understand design and test bench writing :
Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using vhdl or Verilog
by Douglas J. Smith
Also below link is useful
ASIC Design Methodologies and Tools (Digital) :: 21.11.2007 05:24 :: barkha :: Replies: 7 :: Views: 2577
4x4 multiplier can be implemented with a scaling accumulator multiplier which performs multiplication using an iterative shift-add operations.
EDIT: check this pdf which contains 4x4 multiplier
ASIC Design Methodologies and Tools (Digital) :: 28.04.2009 02:57 :: ray123 :: Replies: 4 :: Views: 2714
I want a full adder programming code in vhdl.How can I get software for vhdl programming.How can i get licence for it. Any HELP plz!!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.09.2010 13:03 :: sumati :: Replies: 12 :: Views: 8075
Had just a quick question about a vhdl testbench I made. I am testing a full adder (a,b,c_in are my inputs) and wanted to simply test from (0,0,0 to 1,1,1) as to get all possible combinations of inputs. The reason for this project is just a simple start at vhdl/coding in general.
Anyway my question is this I have this (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.01.2011 18:00 :: Nightlamp :: Replies: 5 :: Views: 1286
this may help u
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.04.2011 00:18 :: pengfefe :: Replies: 1 :: Views: 1827
Hi to all,
i'm studying the vhdl language, and i'm trying to do some exercise!
i did a simple full adder, it works, i have already test it, and with the same criteria i did a ripple carry adder at 8 bits,but i have a problem with the simulation, the error is:
# Loading work.rcatb(tb)
# ** Warning: (vsim-3473) Component (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.04.2011 13:48 :: tj.diego :: Replies: 2 :: Views: 959
Hi, I try to read but it seem like I can't understand it clearly.
Can roughly what does each lines does?
Of course I can, but you won't be any wiser
compare the schematics of the full adder on wikipedia with what has been coded.
Maybe you'll find some similarities. As such you will probably understand it.
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.05.2011 04:05 :: lucbra :: Replies: 19 :: Views: 1784
I am having a problem with my vhdl code made for a multiplication of binary numbers. It keeps showing errors that i do not understand. Is there anyone that could give me a hand, so i upload the program?
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.11.2011 08:37 :: Antros48 :: Replies: 19 :: Views: 2092
You are welcome to see some free projects and vhdl tips at:
vhdl, verilog, design, verification, scripts, ...
Record array in vhdl using free simulator GHDL. record tip
A simple guide describing how to print from vhdl code. print tip
The importance of stop on fata
Embedded Systems and Real-Time OS :: 07.12.2011 07:06 :: pini_1 :: Replies: 3 :: Views: 870
This is an odd quirk from vhdl that annoys most verilog users.
The solution is to create a signal inside your design, eg "cout_buf" and then assign "cout <= cout_buf;".
there are also ways to use a port type of "buffer", but this has other issues when connecting modules, so it is best just to use the extra signal method.
I suggest _buf as the su
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.06.2012 02:17 :: permute :: Replies: 6 :: Views: 1302
There arnt any. You have to build your own or get someone elses. vhdl does not containt libraries of specific constructs, just abstracted ideas as different tools and vendors may do things differently.
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.07.2013 08:26 :: TrickyDicky :: Replies: 5 :: Views: 328
is there anythin specific.. actually there are lotsa things u can implement. wot did u get with the xilinx's developer's kit.. did u get a general purpose kit? if u had purchased a general purpose kit u can try some programs like half, full adder and subtractor, u can also try the MUX and Demux programs..
which version of xilinx webpack did u ge
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.12.2004 19:53 :: arunragavan :: Replies: 4 :: Views: 1352
i got the same problem too. i want to create 4-to1-package mux to built 16-to-1 mux. i've read some tutorial from quartus but could not find the answer.
but i've read from google groups that previous version of quartus did not support the vhdl package. but i'm not sure about the latest version.
anyone know how to solve the probs?
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.12.2006 07:03 :: soloktanjung :: Replies: 3 :: Views: 1468
I am generating post P&R vhdl file from Leonardo.
While compiling it in modelsim error is coming like no default binding for 'ibuf' and 'obuf'.
If I generate same file from the Xilinx then it includes simprim and unisim file. But file generated from Leonardo don't include any such file.
Pls help me
Program is of simple full adder. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.09.2007 23:32 :: gck :: Replies: 0 :: Views: 458
As Iouri suggested, the '-' operator in HDL (such as Verilog or vhdl) is easy to use, and usually generates well-optimized logic for your target device. The results will probably be as small and fast as anything you create yourself.
What is "FA"?
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.10.2007 08:08 :: echo47 :: Replies: 8 :: Views: 628
A delay for output sum might solve.
For vhdl ex:
sum <= ( a xor b ) afte 5 ns ;
carry <= ( a and b ) after 5 ns ;
Analog IC Design and Layout :: 15.04.2008 20:25 :: tomanderson :: Replies: 3 :: Views: 569
I am wondering if it is possible to write a vhdl/verilog code and uses it to generate the schematic and layout so that I can combine it with my own full custom design?
For instance, say I am working on a adder. In order to test the adder, I need to layout not only the adder, but the (...)
ASIC Design Methodologies and Tools (Digital) :: 20.07.2008 13:27 :: pichuang :: Replies: 6 :: Views: 1048
can anyone help the following assignment?
A ripple-carry adder is designed using for-loop construction. The simplest way to describe a ripple-carry adder is to use a chain of 1-bit full-adders (see figure below where 4-bit ripple carry adder is implemented using 1-bit full (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.01.2010 12:35 :: james09 :: Replies: 0 :: Views: 598
I'm new in vhdl and I'm trying to design a modulo generic adder by using ROM. The output for the adder should be (x + y)mod m. I have no idea on how to create it.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.12.2010 19:38 :: energy_baz :: Replies: 3 :: Views: 1200
Here c_out is a signal and carry is a variable. In vhdl, a signal will be updated with a small delay. So dependent assignments like above will not happen in the same clock cycle. But variable will be updated immediately.
For the first clock cycle:
carry(0) := old value of c_out(0) = '1';
c_out(1) <= '1' xor '1' = '0'; --old va
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.06.2011 02:45 :: vipinlal :: Replies: 9 :: Views: 638
I am using TetraMAX to generate test patterns for a full adder code. The problem is at the stage "Write Patterns", Synopsys no longer let us the patterns in Verilog or vhdl, you will receive the error "write_patterns -format verilog_single_file is obsolete; command ignored". I can only save as STIL, binary....But I want to have a (...)
ASIC Design Methodologies and Tools (Digital) :: 22.12.2011 04:03 :: thanhFF :: Replies: 2 :: Views: 655
i need help for my code in test bench ..
the code is
entity ff_vhdl is
Port(a,b : in std_logic_vector(3 downto 0);
cin : in std_logic;
s: out std_logic_vector(3 downto 0);
cout : out std_logic);
architecture structural of ff_vhdl is
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.03.2012 17:47 :: roomy :: Replies: 1 :: Views: 1310
Hello, im practicing on my exam to come, and im trying an old exam, i did answer two questions but im very unsure wether they are correct or not, since it was a long time since i wrote vhdl. I would appreciate if someone could check those answers and tell me if something is wrong :).
a) using vhdl, implement a component for a full (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.05.2012 16:24 :: Ohman :: Replies: 9 :: Views: 333
I want to use some arithmetic operations such as (+,_,*) in my design. The design is fix point. Could you please tell me, If I use (+,_,*) symbols in my vhdl code, is it synthesize correctly or not? Or I need to design the units ( n_bit full adder, for instance) then write the code structurally. ( consider it that, I don't start (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.09.2012 16:12 :: sheikh :: Replies: 6 :: Views: 420
# vsim adder.vhdl
# Loading C:/Modeltech_5.7e/win32/../win32aloem/convert_hex2ver.dll
# ** Error: (vsim-3193) Load of "C:/Modeltech_5.7e/win32/../win32aloem/convert_hex2ver.dll" failed: File not found.
# ** Error: (vsim-PLI-3002) Failed to load PLI object file "C:/Modeltech_5.7e/win32/../win32aloem/convert_hex2ver.dll".
# Region: /
# ** Error:
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.02.2005 09:05 :: deniza :: Replies: 5 :: Views: 4825
have a look there , may be it is within :
there is to_float() function . Check entier directory for float package.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.09.2006 11:56 :: artem :: Replies: 4 :: Views: 1611
I've some interview questions about digital circuit, vhdl and ASIC/FPGA. I think it's a good opportunity for us to discuss these questions. Maybe it's very helpful when we want to seek for jobs in the near future. The following is the first quesion.
Interview question #1:
What are the different adder circuits you studied?
Here is m
ASIC Design Methodologies and Tools (Digital) :: 10.12.2006 01:20 :: richardyue :: Replies: 11 :: Views: 1921
I am looking to design a parallel squarer circuit using vhdl and try optimizing interconnections to see if it can be more efiicient.
The design template Im looking to follow is based on this
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.07.2013 07:52 :: akeedthe :: Replies: 0 :: Views: 251