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46 Threads found on Vhdl Import
I would really appreciate your help. I wrote the following testbench code to test my 6th order FIR filter. It worked perfectly for my behavioral code, but when I try to use it after synthesis for my structural gate-level netlist, I get this error: ERROR:HDLCompiler:1728 - "/home/..." Line 24: Type error near xin ; current type signed; e
Hi. I'm trying to import vhdl source code into Verdi. The source code included user-defined-library file like this library ieee, ZOTLIB ; use ieee.numeric_bit.all ; use ZOTLIB.COMPONENT ; ... The error messsage is like this Can not find library. How can I import library?
Hi Folks, I would like to perform matrix multiplication in vhdl,I have to save the end product in RAM. Thanks in advance.
Maybe you can import vhdl/verilog netlist (synthesized by DC or other tools) directly into virtuoso environment. Then a new schematic will be generated and can be used to do further simulation in ADE. Regards,
Hi, I'm looking for a way to convert a Behavorial description (in vhdl or VERILOG) into a (H)SPICE netlist. I did it in the past with tools from Cadence, but in my current situation I can only use tools from Synopsys. I've tried to look into Design Compiler / Nanosim but I couldn't find anyway of doing that. Is there any other software to do
Information in this page suggests that a function declaration is optional... . The link doesn't talk about packages at all, just functions in general. I see that it doesn't fail a parsing check... Did you also try to import the function in your design? I presu
Ususally, circuits are written in HDL, and often in behavioural form. There is no way to input a K map, just the circuit diagram (which people dont use much, as it cannot be simulated directly). It is much better to use an HDL (vhdl or Verilog).
Alternatively you can build your ISE projects from a Makefile. Then add a rule to update the vhdl file with date & time in it. Essentially it's the same mechanism as that tcl example ... generate a vhdl file with datetime in it.
c <= ('a(3)'&a) + ('b(3)'&b);--to make sign extension. You can also write c <= resize(a,5) + resize(b,5); or even shorter c <= resize(a,5) + b; What I'm doing is because vhdl imposes that the LHS to the equal sign of addition is the same size as the RHS' operands. Will this concatenated bit be r
Respected Sir, I am working on a ASIC on Cadence design tool in Level in my College. Till Now I was Coding in vhdl and successfully simulate it.Now I have to design schematic,layout LVS,RCX and all that post layout simulation work on Cadence tool so that to complete my thesis. My circuit as I get from Technology schematics on Xilinx t
i have a vhdl code ...and we have standard cell in cadence in the front end. How can i import vhdl CODE into cadence and link it with standard cells and simulate it? Pl Help
Hi fellow forum members, As the title suggests, I need to read data from a data file, get the integer values, convert them to two's complement binary and use them as inputs in my vhdl design. My goal is to build a basic signal generator via BASYS2 board and DAC. My plan is to use matlab as an ideal signal sampler, get the functions' values(squar
Hi, is there a way to simulate a vhdl project created in quartus with ISIM of xilinx? I can't compile it in xilinx because it uses pll and other specific functions of altera. Thanks
Hello,I want to import an array (1 x n) to my vhdl code,every element of array is 5-bit.I know I should be use it in serial but I dont know how define input "std_logic or std_logic_vector(4 downto 0)?
I guess, the problem is missing knowledge of the vhdl textio package. Generally ASCII formatted data files are a straightforward way to read in stimulation data. You'll read e.g. one line for each clock cycle in your testbench, and decode one or multiple values and assign it to the stimulus vector. The testbench scans the file line by line and
library ieee; use ieee.std_logic_1164.all; entity updowncounter is generic (n: natural := 8); port ( IC,CLK,upcount,downcount :in std_logic ; Q: out std_logic_vector(n-1 downto 0) ); end updowncounter ; architecture exm1 of updowncounter is begin prc:process (IC,CLK) is variable cnt : unsigned (n-1 downto 0); -
I think you are asking for For vhdl the procedure is the same but you select the vhdl folder and files.
Does Modelsim support use of fixed point? It's no Modelsim problem, the libraries are just vhdl code. Apparently you didn't import the libraries to the simulation project. The altera simulator can only do post place and route simulation. Not quite right. The internal Quartus simulator (available up to V9.1) suppor
I import a vhd file in candece like following: Open icfb. Go to file choose import and then vhdl. Under the file name browser in the vhdlin form go and select the inv vhdl file hit the Add button on the right hand side of the browser window. In the Target Library Name field (...)
I have a synthesised vhdl file with TSMC 180 nm library using Synopsys Design Vision. Now,I want to have the schematic using Cadence Virtuoso.How to do that ?
hello. if i have my own independent vhdl file which i want to import as an ip in my xps project then how can i use GPIOs on the virtex II pro board to talk to my ip?? if i have a multiplier with 2 input ports and a single output port, then how can i send data to these ports using GPIOs??
Hello, I’m trying on using LatticeMico32 as a main CPU aiming to create a CPU that surround by my own peripheral IP module. The problem is when import custom IP module to a system, CPU platform builder (Lattice MSB) supports only Verilog and I know only vhdl. However the manual suggests that vhdl user can create Verilog wrapper to (...)
Depends on the tool you use. If you use Questa, yes, use: vcom -mixedsvvh and then the data types, constants declared in vhdl are visible in SV. There are some restrictions as well, read the user guide. Other tools may not support this, a WA will be to rewrite them in SV (can potentially use a script). HTH Ajeetha, CVC
Hi all, I met a problem. In vhdl file, there are: library unisim; use.unisim.vcomponent.all; When import this file into debussy, error occurs. Debussy can not find unisim lib. So I want the solution, can anyone help me:) Thank u very much! BR weiqi
Hi, There 2 packages in my design, each of them defined a function with exactly the same prototype. How can I specify which one I want to call in my design?
I HAVEN'T BEEN USING THIS XILINX TOOL for quite some time and i decided to re-learn it with version 10 .And wow HOW MUCH THIS TOOL has got sofisticated. There is so much posibilities to design complex systems . I'm trying to completly design software defied radio and import some of the vhdl code to M black boxes . i'm having so much FUN .That all
hi guys.. i need to know how to generate vhdl coding from graphical design in Maxplus2.. i have drwn small simple circuit adder in graphical type, so i wan vhdl codine of it. thanks in advance..
I have synthesize vhdl codes and netlist is i want to import the vhdl(after optimization) of the netlist from cadence so that i start with my physical design. But somehow there was a problem with import and i received an error when i was importing. the error is: duluth: *F,24: logical (...)
Hi While designing FSM we take enumerated there are no other states than what we've defined.still we say when others => idle/default state, why? Isn't it redundant from vhdl point of view? Manasi
Thanks for the reply. The test bench is using vhdl. I am using vhdl to implement my design. Regards, Dhawal
Hi, I assume you mean a RTL-> GDSII flow. In that case you need Modelsim to write your code in vhdl, for synthesis you can use Synopsys tools which will map the libraries according to the process that you are going to use for the chip tapeout. After Synthesis the tool will generate a .v file which you will import in a Place and Route Tool such a
You can use HDL Entry to import your vhdl code and you will see it as hierarchical schematic diagram with easy browsing. There is a trial version:
hi evrey body i want to transfer my vhdl code trough leonardo to l-edit (transistor level) but because of the libraries in the leonardo have not any .TDB library in the l-edit i cant transfer my design if you have the laibrary that have (.SYN) and (.TDB) please upload that and please guid me how to add (.SYN) library to leonardo(the statement t
1. Do you have complete Debussy license? or just nWave license? 2. Please check if you specify topModule, source files and library. To invoke Debussy by command : debussy Some options : - vhdl | verilog : specify language type for import design from source (verilog by default) - top : specify top
Hi, Does anyone know how to import the EDN/NGC netlist file to a vhdl project in Xilinx ISE tool in order to reduce design time? I used to use this method in Altera with VQM netlist files with LogicLock feature. But I did not find any similar way to do that in Xilinx ISE tool. Could anyone give me some suggestion? Thnks
Does Cadence support vhdl-AMS?
If your A/D SFDR is generated by a Simulink model the best way is to write the result in a Matlab workspace and then measure via FFT the SFDR. You can read asci in Dolphin Smash and plot the FFT. If your model is a vhdl-AMS or Spice generate with Smash the best way is to write asci and import in Matlab. All existing Spice's have very limited bac
I use ncsim simulate. thanks. avoid using variables in your vhdl design. VCD file seemed cannot record them
hi, does the ".syn format files"of leonardo spectrum equivalent to .lib files that contain timing information abt cells?if so is it possible to convert to .syn files to vhdl files so that i can import these vhdl libraries and do backannotation. if not using which files does loenardo give the sdf file output?
Is it possible to import HDL (vhdl or Verilog) into ADS? How about C or C++ codes? What i saw in ADS is HDL generation from schematic or design. But i could not find anything about importing HDL (digital design) or C (high level language) codes from outside. Any helps will be appreciated. Thanks in advance, KH
Hi! Can anyone take a look at my project and help me with it. I am trying to import my vhdl and Verilog code via BlackBox and simulate it. but it doesn't work and i don't know why.. :( Anyway I assume that I am missing something.... 10x bart
Since ispLever Base 4.1 doesn't support mixed language designs.. How can I incorporate a vhdl CPU core for example into a Verilog design?
Hi, I am new to Xilinx tools, I was wondering if I have a simple vhdl entity that I'd like to use/test in a edk project a long with a process, how do I import(?) it to the EDK? I'd appreciate if you breifly describe the procedure. Thanks, Mo.
uses command tools: vericom & vhdlcom, cpmille your source code into libraries, then load the libraries into debussy
Hi, Does any one know how to import verilog & vhdl mixed-language design with Debussy? How to edit *.f design list file? my debussy version is 5.2v9, I think it should support this feature. Thanks ahead!
I have a data file of a signal I captured on my oscilloscope, the data contains time and voltage for each measurement. Is it possible to import this text file into Matlab and create a DSP model that uses the data file as input and runs a filter algorithm on it and then somehow using SystemGenerator export that to a vhdl program and dump the whole f