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Vhdl Lookup Table

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19 Threads found on edaboard.com: Vhdl Lookup Table
I need to know how to send saved data in lookup table to audio codec of de2-70 altera kit line out in vhdl.
Do you want to generate the the sin/cos function or a lookup table? If you actually want to generate the function on-the-fly, use a CORDIC. Xilinx has, I believe, a free IP module. I have no idea what that library is; it's certainly not a standard vhdl library that I'm aware of.
i need to use this code ,i post just a small part , it is a very long values , so i need a help in how to use these values which appear below in my code in a lookup table ( ram or rom ), if (outputt<=x"0e00" and outputt>=x"0d7a")then output1<=x"0012"; ----------------------------------------------- elsif (outputt<=x"0d79" and outputt>=x"0c
No, you cannot use std_logic_vector for arithmatic with standard vhdl, because it does not represent a number, just a collection of bits. You should use the the signed and unsigned types instead, and yes multiply and division functions exist for these (but I wouldnt use the divide, because there is no option for pipeling
I am working on vhdl code for Numerically Controlled Oscillator using Xilinx 12.1.When I use the IP core generator to create rom look up table with a depth of 32 values and 15 bit width I have no problems it gets generated. But when I need a depth of 8192 values and 15 bit width the ip core is unable to generate the lookup (...)
at 4b, the best choice will be a lookup table. you can declare that as a constant in vhdl for this size. type int_array is array (natural range <>) of integer; constant MULT_INV : int_array(0 to 15) := (0,1,9,6,13,7,3,5,15,2,12,14,10,4,11,8 ); signal x : integer range 0 to 15; signal y : integer range 0 to 15; ... y <= MULT_INV(x);
I don't understand, what's exactly unsupported in XST. It seems like valid vhdl at first sight. In addition, the code is marked --synthesis translate_off, so it's obviously a simulation tool that would be ignored by XST.
I was thinking e.g. of the Altera DDS compiler, which is basically a core generator, similar to the Xilinx product. The generated core can be included in vhdl or Verilog designs.
I don't need to calculate exactly the Sin() value...only a relative good value of it. A look-up-table would be the most easy solution. It's usually stored in internal ROM that's available with most FPGA families. Cordic is another common method, also taylor series can work. You have to translate the C code to a sequential vhdl pr
Can somebody post a complete table lookup CRC algorithm vhdl code? I can't find any.
Hai! How to convert binary bits (eg."00") to digital symbols(eg."1/sqrt(2) ) using lookup tables in vhdl coding? Can anyone help me out please:-)
anyone tell lookup concept in vhdl?
One possible way is to calculate the table in vhdl at compile time, as shown in the below example. (It's a 0..pi sine table, not the solution for your problem). TYPE SINTAB IS ARRAY(0 TO ROMSIZE-1) OF STD_LOGIC_VECTOR (NNCO-2 DOWNTO 0); SIGNAL SINROM: SINTAB; BEGIN GENROM: FOR idx in 0 TO ROMSIZE-1 GENERATE CONSTANT x: REAL := SI
how can i built a look up table inside fpga based on the data in table below. the table is until data no 4000. please help me. i am new in fpga and vhdl code. thank
Do we have any other structures which can save resource for lookup table by vhdl? Thanks.
Hi all of you! i have a big problem. how can i describe a multiplier using a ROM in vhdl?
can everybody help me to show the sample of vhdl code for sigmoid activation function lookup tables??? :cry::cry:
Hi, Sine and cos waves are generated using Quadrature oscillator. If you integrate sine wave you get cosine wave You integrate this cosine wave to generate input sine wave... This is done using digital filter techniqe here in the vhdl code... Following figure will explain it well.... +----+ +----+ sine | / | -c
lookup table is simply a method to get certain output according to certain input varaible as you get for example telephone number according to input name in your telephone index. it can be implemented in vhdl in many ways for example 1- case starment (as you mention) 2- instantiate a block ram, the address is the input and the memory (...)