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6 Threads found on Vhdl Shift Reg
Hi all, i searched to see if there were other threads that could help me solve this, but found nothing useful enough.. i'm new at vhdl, and i have a problem- i'm supposed to create a generic shift register that also samples the the mid-values (as oppose to just the last output) my problem is that for some reason (i'm probably doing (...)
I got a text paper today, there are 3 questions below that I don't know how to answer them. Can somebody help out? Huge thxs. 1. Design a program with Verilog or vhdl which can detect a series of bits (such as 1010) in a long serial stream. 2. Supposing that you are going to design an electric system. Please describe the design flow from sche
Hello, I asked a similar question earlier to this one except that I wanted to implement a pseudo random binary noise generator using physical hardware. That worked well. Now I am wondering how I would go about implementing one on an EPLD. Does anyone know of where I might go about finding some code written in a form that can be implented on
Not sure exactly if I understand your question. Do you wish to constantly feed the output to something? If so, you can send the output wherever you wish, after a clock edge, the shifted data is present all the time at register ouput. You can either send it to another flip-flop, or you can do continuous assignment so that the output enter into
Try . There You cam find exampoles of E1/T1 framer in vhdl. May be it'll help You.
Typical examples of a shift register description in vhdl and Verilog: -- 4-bit serial-in and serial-out shift register -- CLK: in STD_LOGIC; -- DIN: in STD_LOGIC; -- DOUT: out STD_LOGIC; signal reg: STD_LOGIC_VECTOR(3 downto 0); begin process (CLK) begin if CLK'event and (...)