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6 Threads found on edaboard.com: Vhdl Synthesis Power
Hi, I have written a vhdl code which is synthesized. Now I want to calculate the power without using the power estimator software . i.e. I want to calculate the power using Device utilization summery by using some formula. So, is this possible to calculate????
Hi, I want to synthesis my vhdl code in design compiler.i want to use 90nm libaray.i have wriiten UPF for power gating implementation.. Can anyone tell me which library i should use for this purpose.i have SAEDPDK_EDK folder which contains many library .
dear all i have vhdl code for vga interface, i did all process such as synthesis and implementation so i need to know how i can use Xpower to measure all power ( power by Voltage Supplies,power by User Logic Resources,Thermal Powe) wait your reply regards
Hi all mentors, I am in urgent need of your help as I need to present my project to the professor. I have written a code and synthesized using xilinx and the details are { family: spartan3E Device: XC3S100E package: VQ100 speed: -5 synthesis Tool: XST(vhdl/Verilog) Simulator: Modelsim-XE Verilog Preferred Language: Verilog
vhdl code for leakage power reduction!!!. hmmm I think u should try reading some basics.... vhdl,Verilog describes hardware. Multi Vth cells are selected during synthesis by the synthesis tool. I wonder whether you are asking for the C-code for selection of Multi-Vth cells for (...)
low-power design is not achieved olny just through EDA tools. I have used the powerCompiler, but it is not proved a good way to low-power design!