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Vhdl Testbench Clock

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31 Threads found on edaboard.com: Vhdl Testbench Clock
Hallo, I have simulated the following code using ModelSim. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fifo_SCnt is generic( RAMsize: integer := 256; DataWidth: integer := 8 ); port( clk: in std_logic; rst: in std_logic; data_in: in std_logi
How about using a counter with a 10 Hz clock (1 ms period) or use whatever system clock you have, e.g. 100 MHz clock and create a counter that counts from 0-9,999,999-0 and increment a second counter when you reach 9,999,999 (or at 0,000,001 for a starting increment). Instead of giving the simulator lots of work to do
LIBRARY IEEE; USE ieee.std_logic_1164.all; --USE ieee.std_logic_arith.all; USE ieee.numeric_std.all; library ieee_proposed; use ieee_proposed.fixed_pkg.all; ENTITY dwt IS PORT ( clk : IN STD_LOGIC; vid_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Pixels from main memory hor_sync: IN STD_LOGIC;
I am trying to write a code in vhdl with a given time period of clock in testbench .When i execute it i get proper output , but if i modify the code slightly i.e including more functions (more operations) then although am not changing anything in the test bench , but still i the clock in the test bench waveform appears to have g
Hello All, I am engineering student i want write a code in vhdl go get the simulations as per the picture attached and tried doing that but not getting please help me with the code. thankyou, 123503 123504 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIG
hello, Why the following testbench code in the first clock d1, d2 are value And the second clock a, b library IEEE; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; use IEEE.MATH_REAL.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; library std; use std.textio.all; --in
Hello, x is defined as: signal x: std_logic_vector ( 7 downto 0 ) ; I want 'x' to be incremented by 1 with relation to the simulation time - for example: "00000000" at time: 10 ns "00000001" at time: 20 ns "00000010" at time: 30 ns The obvious will be: x <= "00000000" after 10 ns , "00000001" after 20 ns , "
Hi friends I have the Test Enable signal(TE) 111680 which should be write in vhdl, clkperiod : integer := 4; -- system clock period signal clk : std_logic := '0'; signal te : std_logic := '0'; constant ct : integer := clkperiod/2; clk is already written Can I k
It looks like you are missing a text book like "vhdl for hardware design" or similar. As previously stated, none of the testbench/simulation timing statements works for hardware synthesis. You need to think your design in terms of synthesizable elements, flip-flops and combinational logic. Use a synchronous scheme with a single input (...)
I am trying to convert this vhdl testbench code to verilog testbench, kindly help me to convert this part of code slave_clkedge <= '1' when SLAVE_CPHA = SLAVE_CPOL else '0'; -- Define a 3-bit counter to count SCK edges and data into register so that parallel -- register is loaded. Use same clock (...)
Ok, comments on the code. 1. You should only have clk and reset in the sensitivity list. 2. You should ONLY have if statements for clock and reset in the synchronous process, not anything else. If you want asynchronous code then make another process that is asynchronous. 3. It is best not to and anything with the clock. Put it in a nested if insid
in simulation a code for QAM mapping used in OFDM .. the code is working great but i have a problem the output is shifted by one clock the output that should appear in clk 1 with input11 appears in clk 2 with input 2 and so on the code is this is not clearly my code :) library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOG
Hi, I saw your replies in the forum and felt encouraged to post this question. Thanks for providing your expertise. I have a vhdl test bench that is associated with both implementation and simulation (as I would like to run P&R simulation). I just want to define my clock with a certain time period. Say clock = '1', wait for (...)
1. Yes 2. Its a lot easier to do these checks inside your HDL testbench. For vhdl, the quickest and dirtiest way to stop a testbench is: assert (not end_of_sim) report "Simulation finished!" severity failure; Although the cleanest way is to stop all stimulus - ie. halt input processes and turn the clock off. 3. You cant (...)
hello, I'm trying to creaet a test bench for my program which I wrote in vhdl all my inputs are stored in an array, so I don't have any input declared in the entity that makes me wonder how I can change the value in my test bensh, note that in my module I have a FOR LOOP, and some IF condition, how can I integrate it in the test bench??
im trying to display a red box on a 640 by 480 screen however nothing is displayed on my vga screen im using nexys 3 and these were the port used clk v10 ns-n6 vs -p7 red1 -u7 green2 - p8 blue2 -r7 here under is my code which i made thanks i appriate any help library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
Hi all, one of my vhdl modules produces "X" values even with the slowest clock; there were no problems with its behavioral simulation though. Here's the code; basically it's an adder (it sums its single data input A2 to a constant FO1 after reshaping A2 into the variable A1) whose output is forced to 0 if the result is negative ent
I guess, the problem is missing knowledge of the vhdl textio package. Generally ASCII formatted data files are a straightforward way to read in stimulation data. You'll read e.g. one line for each clock cycle in your testbench, and decode one or multiple values and assign it to the stimulus vector. The testbench scans (...)
Hello, I have designed that code. you can find it on
My vhdl program seems to work when I remove the external clock, but when I add the clock to the RS 232 Reciever Code, It doesn't work anymore in the testbench. I'm trying to make a UART application, PC to Spartan 3E, my PC (hyperterminal is set to 9600 baud rate) so I have to supply the clock RX DCE from (...)
Hello to everybody! I'm new on programming FPGA and i have a question about a problem i can't resolve when i'm testbenching my component: The project is a driver for the LCD installed on the evaluation board; below there is the part of the code that got me problems and in particular it is on the signal data_lcd (declared as inout). When i si
Check my post in the following link (vhdl code & testbench , simulation result) The method i have used is described in this link . The other solution is a dual-edge triggered flip-flop but you will not find it in many devices, for e
Hi, everyone! I'm a beginner at vhdl coding. Recently in a project, we need to transfer data between two clock domains. These two clocks probably at the same frequency but with asynchronous phase. So I use async FIFO. The attachments include the vhdl codes and the testbench (not perfect). I don't know if (...)
Hi, In C-based verification environment (Assume testbench, Testcases and all environment components like Monitor, Checker, Score-boards all are written in C, DUT is written either Verilog/vhdl) how to create clock Source? In such a verification environment is there any other difficulties to be faced? Please answer this question, since I'm (...)
I have a module with one architecture and in the behavioral simulation, I get the result that I want. But when I use an instance of this module in a new module, the simulation(with the same input values, Ive checked the intern signals) gives a different result (the output is one cycle delayed). Can anyone help me?
Hi, Can anyone tell me how to write testbench for clock with offset. Here is my test bench process begin clk1 <= '1'; wait for 10ns; clk1 <= '0';wait for 10ns; end process; process begin clk2 <= '0';(other signal);wait for 5ns; clk2 <= '1';(others signal);wait for 10ns; clk2 <= '0';(others signal);wait for 10ns; ...u
hello everyone, i have written the code beneath in vhdl for a mupltiply accumulator and while it is coming in FPGA port, the led don't provide with the correct result. is there anyone who knows what the problem is? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity olok
Hi , I have a problem ... I must generate a time diagram to control a ADC... But it have a difficult time diagram, can somebody help me to understand, what's the best metod in vhdl to create a time diagram (NO testbench)... How can I start from a clock and generate a time diagram with fix delay ? thanks
Hi, I am designing a decimation filter for a data standard like ardis or mobitex. since there is a lot of upsampling and downsampling going on so i need multiple clocks all the way in my pipeline. How can i write different clocks for my test bench. I am confused about how can i associate different frequencies with different components in my to
Hi I use ISE6.3 and i have input clk100Mhz and i want to generate 2 outputs one 25Mhz and other 50Mhz if free IPcore in vhdl is available. Thank's
hello out there how can i make a big delay like 1,10,15 sec for example if i want my output to go high after 10 secs from the incoming signal on my input ??? should i make counter module ?? Need some guide and some coding example if posible thx