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310 Threads found on edaboard.com: Vhdl Testbench
hello everyone, I am trying to set up a vhdl testbench for my project in Vivado. I want to make a simulation from the top level perspective and not just simulating an IP core. Vivado already added the HDL wrapper for the simulation, but I'd rather use my own testbench instead of the wrapper. I started creating a new file, copied and (...)
Hallo, I have simulated the following code using ModelSim. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fifo_SCnt is generic( RAMsize: integer := 256; DataWidth: integer := 8 ); port( clk: in std_logic; rst: in std_logic; data_in: in std_logi
Upto Line nos 108 is visible. There are numerous eg of vhdl file read floating around. Study one of them and compare it with your code. begin . . process file file_pointer : text; . . begin . . --Open the file write.txt from the specified location for writing(WRITE_MODE). file_open(file_pointer
Hello everyone. I want to use some data from external file in my testbench. Loading data from file: ------------------------------------------ --LOADING DATA FROM FILE----------- ------------------------------------------ type signal_storage is array (integer range <>)of std_logic_vector (data_width-1 downto 0); signal mem : signa
First off, if you're new to vhdl, I suggest you stay away from variables entirely. There is nothing you can do with variables that you cannot do with a signal. Signals will give you behaviour you expect, whereas variables do have some gotchas with them. Without a testbench, it can be difficult to see whats going wrong. With simulation you can ea
Aren't vhdl or System Verilog enumeration types decoded by your simulator?
Many years ago some one told me that it is better to have a verilog/SV testbench for GLS rather than vhdl. Can some one please explain me why ? best regards Simon
As mentioned above writing a test-bench in Verilog/vhdl is the best way to do it. Another crude method would be to force the desired input signals and see the output. This processes is highly discouraged!
Hello, begin p_fmcw : process(reset_n_i, clk_128m_i) begin if (reset_n_i = '0') then temp_s <= 0; cnt_s <= '0'; elsif (clk_128m_i'event and clk_128m_i = '1') then if (enable_i = '1' and fmcw_trig_i = '1') then if (temp_s = 0) then temp_s <= temp_s + to_integer(unsigned(fstep_
How about using a counter with a 10 Hz clock (1 ms period) or use whatever system clock you have, e.g. 100 MHz clock and create a counter that counts from 0-9,999,999-0 and increment a second counter when you reach 9,999,999 (or at 0,000,001 for a starting increment). Instead of giving the simulator lots of work to do
No. I am pretty new to vhdl. I am still learning my way around the Xilinx ISE and vhdl as such. I am in the process. In the mean time if someone could comment on the query it ll be helpful
for a testbench: process begin wait for 1s; --do something wait for 1s; -- do something else --etc end process; Note that this code is ONLY for testbenches. It cannot be used on a chip because circuits have no understanding of time. In a real circuit you would have to build a counter and enable.
Without seeing the netlist and/or the simulation testbench we can only guess. You mention in your first post that you did a behavioral simulation of the vhdl. Are you using the same testbench for both the behavioral and netlist simulation? - - - Updated - - - Also are you sure that there isn't a GSR i
LIBRARY IEEE; USE ieee.std_logic_1164.all; --USE ieee.std_logic_arith.all; USE ieee.numeric_std.all; library ieee_proposed; use ieee_proposed.fixed_pkg.all; ENTITY dwt IS PORT ( clk : IN STD_LOGIC; vid_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Pixels from main memory hor_sync: IN STD_LOGIC;
I am trying to write a code in vhdl with a given time period of clock in testbench .When i execute it i get proper output , but if i modify the code slightly i.e including more functions (more operations) then although am not changing anything in the test bench , but still i the clock in the test bench waveform appears to have g
Hello, Could you pls helm me with cordic vhdl testbench for this code
Can any one help me declare a variable array. in avhdl for a papilio one
All numbers that calculated are pseudorandom. Even if you feed them with the system time, the resulting sequence is psuedorandom, based on a given distribution. Getting truly random input in a vhdl testbench would be very difficult, as it would hard to hook into a RNG system function (which usually uses something like thermal noise to create a rand
How do we create a testbench in vhdl AMS? The platform I have used is Hamster vhdl
Hello All, I am engineering student i want write a code in vhdl go get the simulations as per the picture attached and tried doing that but not getting please help me with the code. thankyou, 123503 123504 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIG
The concept it simple - you use your entity as a component and inject it with software generated stimuli. You then observe the behavior of the design as it responds to the given stimuli. As TrickyDicky mentioned - there's a lot of information available. Try this: Also, you c
I created a test bench where i want to test the interaction between 2 components, but for some reason does my testbench not recognize my head (topmodule). which has all my components. Some form of clarification would help here. testbench: head_tb.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library
hello, Why the following testbench code in the first clock d1, d2 are value And the second clock a, b library IEEE; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; use IEEE.MATH_REAL.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; library std; use std.textio.all; --in
Hello, I want to describe in vhdl a generator parallel 4 bits to serial 1 bit. Indeed, at each clock edge (250 kHz), we take only one bit starting with the least significant bit (LSB). Example: Input = "0101" (over 4 bits) So at first clock edge, output = '1' (LSB) Second clock edge, output = '0' Third clock edge, output = '1' Fourth clock
Hello I have written the alu programm for adder, multi, divisor, subtractor. I am getting output also but the output is not right. Can anyone help me out by checking the ? LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- Entity for ALU component
I use quartus ii and model sim altera se. When i write a test bench file it consists of some code lines related to timing. Than when i compile it and run simulation does this substitute a timing simulation ? Or do i have to involve .sdo file into the simulation in all conditions for a timing simulation? For example what kind of simulation i
------------------------------ -------------------------------- library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use IEEE.std_logic_textio.all; package butter_lib is signal ram_data,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,out_data : std_logic_vector(31 downto 0) := (others => '0') ; sig
I am getting this error ERROR:Xst:841 - "H:/Carry increment/carryincrement/carryincrement.vhd" line 98: Bad condition in wait statement, or only one clock per process. 117283
i tried to multiply two numbers in xilinx using vhdl. The program has no errors but when it comes to viewing the results, when the MSB of one or both the numbers is '1', then the data is not getting read (it is showing undefined symbol). But when the MSB of both the numbers is '0', then both the data can be read and it is giving appropriate result
Maybe get rid of the gated clock altogether as a first step. That is a big no-no in FPGAs, especially if you would like to implement a design that works. StopCount should be implemented as an enable. Also the if statement should have as the else clause the entire code from the counter assignment to the end of the case. I've always gone by the ru
Hi, I am a newcomer but i need help to update an existed vhdl code below with 3 colors on the screen to a screen without color and image if no pen points it for a VmodTFT of XIlinx: ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_A
Hi there, i have a problem with my vhdl testbench. i have an ip-core generated in verilog-code, wrapped and instantiated in my tb. However, i get the following message in the simulator console: "PUR_INST.PURNET" from module "tb.Inst_top.u1_dut.xjc8ae8.epa4aa7.baa8f3b" (module not found) the core also includes a verilog testbench (...)
Seems like you want to do this as part of a testbench? I'm assuming you know that vhdl is a hardware description language and you can't synthesize file I/O operations into hardware. Regardless of your intent...You could have used google like I did:
Hi I Am giving 16 inputs in a text file for a certain vhdl code . these inputs are coming one by one. Can I consider them as 4*4 matrix Form?? If you want to. You can also consider it as a stream of ones and zero's You can use them however you want - it's your design.
How to add, subtract and multiply floating point complex numbers???? i m workin on sphere decoder and have to use complex no. ....... pls..help Somebody has probably already created such a package, I would suggest using Google to try to find it rather than re-inventing it. But if you want to create it from s
I am doing 2D fft in vhdl . My algorithm is 1) 1D fft then 2) transpose of the output of 1D fft 3)again 1D ft of those transpose output 4)again transpose the 1D fft Are you sure this is the correct algorithm? I ran across this method on sta
hi, i am new to vhdl. I have written a test bench which read real Data from a text file,store it in a array in vhdl testbench. Then i have converted it into Std_logich vector and store this new data in another array. I need to feed this array as Input to my testbench. I have done this with following code. type mem is (...)
Is it really a C testbench that interacts with the vhdl code during run time? or just a C model that generates test vectors? The former would be quite a rare thing (and I suggest speaking to the original author to see how (s)he got it working)
Hello, x is defined as: signal x: std_logic_vector ( 7 downto 0 ) ; I want 'x' to be incremented by 1 with relation to the simulation time - for example: "00000000" at time: 10 ns "00000001" at time: 20 ns "00000010" at time: 30 ns The obvious will be: x <= "00000000" after 10 ns , "00000001" after 20 ns , "
Hello, I am a basic user of vhdl and wanted to know if there is any vhdl equivalent of systemverilog. Thanks, Hobbyiclearner
Hi friends I have the Test Enable signal(TE) 111680 which should be write in vhdl, clkperiod : integer := 4; -- system clock period signal clk : std_logic := '0'; signal te : std_logic := '0'; constant ct : integer := clkperiod/2; clk is already written Can I k
Hello all. I'm new to vhdl programming so please forgive me in advance if i ask any bad question. I have an assignment to create a vhdl model and testbench for SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT device. I have started reading up as much as i can and time is running out. OK, that is the problem statement... [
It looks like you are missing a text book like "vhdl for hardware design" or similar. As previously stated, none of the testbench/simulation timing statements works for hardware synthesis. You need to think your design in terms of synthesizable elements, flip-flops and combinational logic. Use a synchronous scheme with a single input clock th
I have written a vhdl code for a number of cascaded mux stages. During simulation it is observed that the syntax is succesfull and RTL schematic is generated. But I can't implement the test bench waveform. If any one know how to fix this please help me . It is urgent. I'm attaching the code with this. package body ---------------
Hello guys! i have implemented the following online adder for signed digit using vhdl code and i have simulated my design according to the example table shown in the figure attached the problem is i am not getting the first result which is "10" for Z+ and Z+ and at some point a combination of XX and YY gives different ZZ 109982
I have HDL code for a statemachine type of circuit. I am writing a testbench for it. At the moment I provide it with inputs and than after clk cycle delays use vhdl assert statements on each output of the circuit. This way I have an automatic testbench which shall produce a failure message if any assert statement fails. However, I think (...)
I have some real numbers like 9.123472e+002. I need to print these to a file after converting them to normal decimal number representation from scientific representation like in this example I want to write 912.3472 to the file instead of writing 9.123472e+002. Any idea how to do this in vhdl? Any library functions to do this job?
Here is the brief explanation of my project.(Efficient built in self repair strategy for embedded SRAM using selectable redundancy) The project deals with testing of a memory before using it. The memory contains 64 locations(6 address lines),4bit data in it.6 redundancy locations for reparing purpose.(58 to 63 are redundancy test th
hi im trying to make an image processor using virtex5, and im using modelsim for simulation tool. my question is, in testbench file, how to read multiple sequential images? i can open and read 1 frame image but dont know how to do when the next frame is needed. this is part of my test bench code .... initial begin
So what is the problem? Can you post the testbench? why cant you just put a sign bit on the front of the unsigned number? the problem here is you're using the non-standard std_logic_signed library, so you cannot do signed and unsigned arithmatic in the same file. You need to use the signed/unsigned types from numeric_std, and then you have no probl