310 Threads found on edaboard.com: Vhdl Testbench
I am trying to set up a vhdl testbench for my project in Vivado. I want to make a simulation from the top level perspective and not just simulating an IP core. Vivado already added the HDL wrapper for the simulation, but I'd rather use my own testbench instead of the wrapper.
I started creating a new file, copied and (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-01-2017 10:28 :: MOd24 :: Replies: 3 :: Views: 686
I have simulated the following code using ModelSim.
entity fifo_SCnt is
RAMsize: integer := 256;
DataWidth: integer := 8
clk: in std_logic;
rst: in std_logic;
data_in: in std_logi
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-25-2017 15:07 :: muhammad_ali :: Replies: 4 :: Views: 489
Upto Line nos 108 is visible.
There are numerous eg of vhdl file read floating around. Study one of them and compare it with your code.
file file_pointer : text;
--Open the file write.txt from the specified location for writing(WRITE_MODE).
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-20-2017 21:02 :: dpaul :: Replies: 5 :: Views: 509
Hello everyone. I want to use some data from external file in my testbench.
Loading data from file:
--LOADING DATA FROM FILE-----------
type signal_storage is array (integer range <>)of std_logic_vector (data_width-1 downto 0);
signal mem : signa
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-27-2016 19:50 :: ustinoff :: Replies: 1 :: Views: 744
First off, if you're new to vhdl, I suggest you stay away from variables entirely. There is nothing you can do with variables that you cannot do with a signal. Signals will give you behaviour you expect, whereas variables do have some gotchas with them.
Without a testbench, it can be difficult to see whats going wrong. With simulation you can ea
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-25-2016 09:50 :: TrickyDicky :: Replies: 31 :: Views: 2401
Aren't vhdl or System Verilog enumeration types decoded by your simulator?
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-18-2016 12:36 :: FvM :: Replies: 6 :: Views: 580
Many years ago some one told me that it is better to have a verilog/SV testbench for GLS rather than vhdl.
Can some one please explain me why ?
ASIC Design Methodologies and Tools (Digital) :: 09-06-2016 12:32 :: sythe :: Replies: 1 :: Views: 472
As mentioned above writing a test-bench in Verilog/vhdl is the best way to do it.
Another crude method would be to force the desired input signals and see the output. This processes is highly discouraged!
Software Problems, Hints and Reviews :: 08-29-2016 14:22 :: dpaul :: Replies: 2 :: Views: 566
p_fmcw : process(reset_n_i, clk_128m_i)
if (reset_n_i = '0') then
temp_s <= 0;
cnt_s <= '0';
elsif (clk_128m_i'event and clk_128m_i = '1') then
if (enable_i = '1' and fmcw_trig_i = '1') then
if (temp_s = 0) then
temp_s <= temp_s + to_integer(unsigned(fstep_
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-29-2016 07:07 :: Vijay Vinay :: Replies: 0 :: Views: 44
How about using a counter with a 10 Hz clock (1 ms period) or use whatever system clock you have, e.g. 100 MHz clock and create a counter that counts from 0-9,999,999-0 and increment a second counter when you reach 9,999,999 (or at 0,000,001 for a starting increment).
Instead of giving the simulator lots of work to do
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-25-2016 15:38 :: TrickyDicky :: Replies: 7 :: Views: 717
No. I am pretty new to vhdl. I am still learning my way around the Xilinx ISE and vhdl as such. I am in the process. In the mean time if someone could comment on the query it ll be helpful
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-15-2016 20:20 :: arve9066 :: Replies: 4 :: Views: 600
for a testbench:
wait for 1s;
wait for 1s;
-- do something else
Note that this code is ONLY for testbenches. It cannot be used on a chip because circuits have no understanding of time. In a real circuit you would have to build a counter and enable.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-04-2016 11:59 :: TrickyDicky :: Replies: 1 :: Views: 313
Without seeing the netlist and/or the simulation testbench we can only guess.
You mention in your first post that you did a behavioral simulation of the vhdl. Are you using the same testbench for both the behavioral and netlist simulation?
- - - Updated - - -
Also are you sure that there isn't a GSR i
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-31-2016 22:52 :: ads-ee :: Replies: 3 :: Views: 576
ENTITY dwt IS
clk : IN STD_LOGIC;
vid_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Pixels from main memory
hor_sync: IN STD_LOGIC;
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-29-2016 06:32 :: 214 :: Replies: 5 :: Views: 577
I am trying to write a code in vhdl with a given time period of clock in testbench .When i execute it i get proper output , but if i modify the code slightly i.e including more functions (more operations) then although am not changing anything in the test bench , but still i the clock in the test bench waveform appears to have g
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-13-2016 06:29 :: xtcx :: Replies: 7 :: Views: 715
Could you pls helm me with cordic vhdl testbench for this code
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-12-2016 14:21 :: Kosyas41 :: Replies: 0 :: Views: 1
Can any one help me declare a variable array. in avhdl for a papilio one
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-14-2016 08:41 :: fisat :: Replies: 1 :: Views: 440
All numbers that calculated are pseudorandom. Even if you feed them with the system time, the resulting sequence is psuedorandom, based on a given distribution. Getting truly random input in a vhdl testbench would be very difficult, as it would hard to hook into a RNG system function (which usually uses something like thermal noise to create a rand
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-18-2016 11:26 :: TrickyDicky :: Replies: 4 :: Views: 1397
How do we create a testbench in vhdl AMS? The platform I have used is Hamster vhdl
PCB Routing Schematic Layout software and Simulation :: 12-29-2015 15:26 :: Arushi Jain :: Replies: 0 :: Views: 411
I am engineering student i want write a code in vhdl go get the simulations as per the picture attached and tried doing that but not getting please help me with the code.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-26-2015 09:57 :: Anupama shetter :: Replies: 1 :: Views: 506
The concept it simple - you use your entity as a component and inject it with software generated stimuli. You then observe the behavior of the design as it responds to the given stimuli.
As TrickyDicky mentioned - there's a lot of information available.
Also, you c
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-24-2015 16:08 :: shaiko :: Replies: 2 :: Views: 531
I created a test bench where i want to test the interaction between 2 components, but for some reason does my testbench not recognize my head (topmodule). which has all my components.
Some form of clarification would help here.
-- Uncomment the following library
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-24-2015 09:50 :: kidi3 :: Replies: 3 :: Views: 628
Why the following testbench code in the first clock d1, d2 are value
And the second clock a, b
use std.textio.all; --in
Digital Signal Processing :: 08-28-2015 18:17 :: esielec :: Replies: 1 :: Views: 620
I want to describe in vhdl a generator parallel 4 bits to serial 1 bit.
Indeed, at each clock edge (250 kHz), we take only one bit starting with the least significant bit (LSB).
Input = "0101" (over 4 bits)
So at first clock edge, output = '1' (LSB)
Second clock edge, output = '0'
Third clock edge, output = '1'
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-02-2015 18:03 :: isamel85 :: Replies: 6 :: Views: 687
Hello I have written the alu programm for adder, multi, divisor, subtractor.
I am getting output also but the output is not right.
Can anyone help me out by checking the ?
-- Entity for ALU component
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-31-2015 11:16 :: abhiinics :: Replies: 2 :: Views: 628
I use quartus ii and model sim altera se.
When i write a test bench file it consists of some code lines related to timing. Than when i compile it and run simulation does this substitute a timing simulation ?
Or do i have to involve .sdo file into the simulation in all conditions for a timing simulation?
For example what kind of simulation i
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-26-2015 15:59 :: kemalkemal :: Replies: 4 :: Views: 733
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package butter_lib is
signal ram_data,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,out_data : std_logic_vector(31 downto 0) := (others => '0') ;
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-18-2015 09:41 :: vhdlpro :: Replies: 2 :: Views: 758
I am getting this error
ERROR:Xst:841 - "H:/Carry increment/carryincrement/carryincrement.vhd" line 98: Bad condition in wait statement, or only one clock per process.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-08-2015 02:13 :: Arrowspace :: Replies: 4 :: Views: 1029
i tried to multiply two numbers in xilinx using vhdl. The program has no errors but when it comes to viewing the results, when the MSB of one or both the numbers is '1', then the data is not getting read (it is showing undefined symbol). But when the MSB of both the numbers is '0', then both the data can be read and it is giving appropriate result
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-16-2015 12:09 :: sumod :: Replies: 2 :: Views: 504
Maybe get rid of the gated clock altogether as a first step. That is a big no-no in FPGAs, especially if you would like to implement a design that works. StopCount should be implemented as an enable.
Also the if statement should have as the else clause the entire code from the counter assignment to the end of the case. I've always gone by the ru
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-14-2015 15:10 :: ads-ee :: Replies: 6 :: Views: 1057
I am a newcomer but i need help to update an existed vhdl code below with 3 colors on the screen to a screen without color and image if no pen points it for a VmodTFT of XIlinx:
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-07-2015 05:21 :: mmrong :: Replies: 5 :: Views: 796
i have a problem with my vhdl testbench. i have an ip-core generated in verilog-code, wrapped and instantiated in my tb.
However, i get the following message in the simulator console:
"PUR_INST.PURNET" from module "tb.Inst_top.u1_dut.xjc8ae8.epa4aa7.baa8f3b" (module not found)
the core also includes a verilog testbench (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-26-2015 17:59 :: LatticeSemiconductor :: Replies: 7 :: Views: 1378
Seems like you want to do this as part of a testbench? I'm assuming you know that vhdl is a hardware description language and you can't synthesize file I/O operations into hardware.
Regardless of your intent...You could have used google like I did:
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-18-2015 16:23 :: ads-ee :: Replies: 3 :: Views: 1095
I Am giving 16 inputs in a text file for a certain vhdl code . these inputs are coming one by one.
Can I consider them as 4*4 matrix Form??
If you want to.
You can also consider it as a stream of ones and zero's
You can use them however you want - it's your design.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-07-2015 06:59 :: TrickyDicky :: Replies: 4 :: Views: 1096
How to add, subtract and multiply floating point complex numbers????
i m workin on sphere decoder and have to use complex no. .......
Somebody has probably already created such a package, I would suggest using Google to try to find it rather than re-inventing it. But if you want to create it from s
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-14-2015 14:22 :: K-J :: Replies: 11 :: Views: 1662
I am doing 2D fft in vhdl . My algorithm is
1) 1D fft then
2) transpose of the output of 1D fft
3)again 1D ft of those transpose output
4)again transpose the 1D fft
Are you sure this is the correct algorithm? I ran across this method on sta
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-20-2015 00:03 :: ads-ee :: Replies: 5 :: Views: 1017
i am new to vhdl. I have written a test bench which read real Data from a text file,store it in a array in vhdl testbench. Then i have converted it into Std_logich vector and store this new data in another array.
I need to feed this array as Input to my testbench. I have done this with following code.
type mem is (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-13-2015 12:28 :: harian :: Replies: 7 :: Views: 1217
Is it really a C testbench that interacts with the vhdl code during run time? or just a C model that generates test vectors?
The former would be quite a rare thing (and I suggest speaking to the original author to see how (s)he got it working)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-12-2015 11:08 :: TrickyDicky :: Replies: 5 :: Views: 780
x is defined as:
signal x: std_logic_vector ( 7 downto 0 ) ;
I want 'x' to be incremented by 1 with relation to the simulation time - for example:
"00000000" at time: 10 ns
"00000001" at time: 20 ns
"00000010" at time: 30 ns
The obvious will be:
"00000000" after 10 ns ,
"00000001" after 20 ns ,
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-23-2014 16:37 :: shaiko :: Replies: 4 :: Views: 740
I am a basic user of vhdl and wanted to know if there is any vhdl equivalent of systemverilog.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-19-2014 10:56 :: hobbyiclearner :: Replies: 11 :: Views: 1995
I have the Test Enable signal(TE) 111680 which should be write in vhdl,
clkperiod : integer := 4; -- system clock period
signal clk : std_logic := '0';
signal te : std_logic := '0';
constant ct : integer := clkperiod/2;
clk is already written
Can I k
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-25-2014 23:18 :: abu9022 :: Replies: 1 :: Views: 731
Hello all. I'm new to vhdl programming so please forgive me in advance if i ask any bad question. I have an assignment to create a vhdl model and testbench for SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT device. I have started reading up as much as i can and time is running out.
OK, that is the problem statement...
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-31-2014 10:45 :: K-J :: Replies: 3 :: Views: 742
It looks like you are missing a text book like "vhdl for hardware design" or similar.
As previously stated, none of the testbench/simulation timing statements works for hardware synthesis.
You need to think your design in terms of synthesizable elements, flip-flops and combinational logic. Use a synchronous scheme with a single input clock th
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-26-2014 10:20 :: FvM :: Replies: 12 :: Views: 1163
I have written a vhdl code for a number of cascaded mux stages. During simulation it is observed that the syntax is succesfull and RTL schematic is generated. But I can't implement the test bench waveform. If any one know how to fix this please help me . It is urgent. I'm attaching the code with this.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-21-2014 08:28 :: rekhavp :: Replies: 3 :: Views: 895
i have implemented the following online adder for signed digit using vhdl code
and i have simulated my design according to the example table shown in the figure attached
the problem is i am not getting the first result which is "10" for Z+ and Z+ and at some point a combination of XX and YY gives different ZZ
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-04-2014 12:44 :: ghattas.akkad :: Replies: 5 :: Views: 992
I have HDL code for a statemachine type of circuit. I am writing a testbench for it. At the moment I provide it with inputs and than after clk cycle delays use vhdl assert statements on each output of the circuit. This way I have an automatic testbench which shall produce a failure message if any assert statement fails.
However, I think (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-30-2014 19:34 :: matrixofdynamism :: Replies: 5 :: Views: 1666
I have some real numbers like 9.123472e+002.
I need to print these to a file after converting them to normal decimal number representation from scientific representation like in this example I want to write 912.3472 to the file instead of writing 9.123472e+002.
Any idea how to do this in vhdl? Any library functions to do this job?
ASIC Design Methodologies and Tools (Digital) :: 08-12-2014 11:28 :: raghava216 :: Replies: 6 :: Views: 1208
Here is the brief explanation of my project.(Efficient built in self repair strategy for embedded SRAM using selectable redundancy)
The project deals with testing of a memory before using it. The memory contains 64 locations(6 address lines),4bit data in it.6 redundancy locations for reparing purpose.(58 to 63 are redundancy test th
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-11-2014 05:44 :: Swathi k :: Replies: 9 :: Views: 865
im trying to make an image processor using virtex5, and im using modelsim for simulation tool.
my question is,
in testbench file, how to read multiple sequential images?
i can open and read 1 frame image but dont know how to do when the next frame is needed.
this is part of my test bench code
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-03-2014 07:43 :: kissmoh :: Replies: 4 :: Views: 783
So what is the problem? Can you post the testbench? why cant you just put a sign bit on the front of the unsigned number? the problem here is you're using the non-standard std_logic_signed library, so you cannot do signed and unsigned arithmatic in the same file. You need to use the signed/unsigned types from numeric_std, and then you have no probl
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-22-2014 07:06 :: TrickyDicky :: Replies: 6 :: Views: 1988