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13 Threads found on edaboard.com: Voltage Divider Cmos
Hi, For 6V types you may look for CD4xxx type cmos ICs. You may also use a voltage divider to decrease input voltage, then you coukd use the more common HC or HCT type circuits. But what do you mean with 200 ...250mA input? A logic is usually built for very low input current, in most cases below microamperes. If you need (...)
Hello. I'm trying to design a circuit using active voltage divider(with op amps) instead of a passive one, because i'm use the same channel for both CAN signal and Programming voltage, and the passive voltage is in this channel, and is somehow messing with CAN signal. i already fixed the problem for now, but still need an (...)
If both devices works at same voltage level no need to worry you can connect directly. If one is at 3.3v and another is at 5v and if it is UART interfacing (RX, TX) you can use simple resistor divider to connect the Tx of 5v chip to Rx of 3.3v chip. Connect directly the 3.3v Tx to Rx of 5v chip. (For cmos high is >= 2/3Vdd to Vdd which (...)
Most digital cmos 4000 series ICs have a maximum voltage of 18V and some (Texas Instruments) have 22V.
That is not solution Your answer suggests that you didn't yet get the idea of a clamp circuit, as proposed by alex (and typically used in industry standard equipment). A clamp circuit is different from a voltage divider. It's placed in front of a high impedance input, e.g a cmos buffer, and only reducing the voltage if (...)
Hello, You can use a simple voltage divider to Feed a cmos buffer such as CD4050 and then take the 5 Volt output. Since CD4050 is cmos and power with 5V its good for your output. But for the input you have 0-12V so you require to reduce it to some 4 or 5V . This is easily achieved using a proportional (...)
i have designed a voltage divider circuit with a buffer and a resistor divider, the input is from the PTAT(about 1.24V),when the generated reference voltage Vcm (0.9V)is connected to the actual circuit(a pipelined adc in sample phase),the value of Vcm changes a little(about 16mV),so the circuit can't work properly; later (...)
I think the second order effect of the mos make the accuracy of the voltage very low. however, the resistor used in voltage divider circuit has better relative accuracy.
I designed a PLL in cmos and now is doing the testing. It is weird whenever I turn on the reference clock, the control voltage of VCO goes to VDD (1.2V) immediately. This happens even when the charge pump current is zero. I do not know what is going on.
this would be a push-pull amplifier Hey, In the basis cmos inverter ( having NMOS and PMOS ) what ll happen when both the transistors r in saturation and what ll be the output.. Will the circuit behaves as voltage divider in this case???.. Can u explain in detail.. Thanks in advance.
What could of amplifier are you using at the CMFB(the one used to bias the active loads) ? Check its input, may be it sinks or sources current that flows through the potential divider resistors causing that voltage difference between the common mode level and Vref . Try using an ideal amplifier or a single ended o/p cmos differential (...)
HI, I am designing a cmos PLL (Tri-state pfd, charge pump, divider, vco). The divider is a swallow divider, so I can choose different dividing ratio (or different channel). It works at the first channel (dividing ratio is 464). But for the highest channel (dividing ratio is 478), it can not lock. The control (...)
Yes, if you use one diode connected you'll obtain one bias voltage. But YOU could use MORE diode connected transistors in the same branch (same current) to obtain other bias voltage. If you are working on cmos you could try with pmos or nmos acording which bias voltage you need.