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94 Threads found on Weak Pull Up
I don't think it is possible to disable the weak pullups on this micro. It is basically an 80C32, where the pullups are always on, to allow the I/O pins to function as both inputs and outputs, simply by clearing the port latch; there is no data direction register. Is it really that important to have the pullup disabled? (...)
Hi, I face some problems in designing a full CMOS SRAM cell: 1. The choose of W/L ratio The W/L of the back-to-back inverters should be the same? I saw this in somewhere. I was confuse by that because in a latch, the forward inverter should be stronger than the feedback inverter... The Wordline transistor should have smaller W/L com
Hi, I face some problems in designing a full CMOS SRAM cell: 1. The choose of W/L ratio The W/L of the back-to-back inverters should be the same? I saw this in somewhere. I was confuse by that because in a latch, the forward inverter should be stronger than the feedback inverter... The Wordline transistor should have smaller W/L compare
if you want 20 mA you need to set it to 'output' and assert a high on that pin.... the internal pull-up (weak pull-up) is only for 'input' mode on that pin... note also that if a pin can source 20mA all the pins can't source more than 100mA or all the ports more than 200mA (of course it depends on your microcontroller (PIC? AVR?), but (...)
Another question,usually,what's the internal pull-up resistor value can be called weak pull-up?
No, a weak pull-down is a large resistance (or equivalent, i.e. it might be an active device on a chip), as high a resistance as possible which overrides any leakage currents to guarantee a valid logic 0 voltage. Smaller values would waste power when driven high, higher values would not guarantee a logic 0.
No. The pull-up resistor only acts as a "weak" pull-up source. So when slave drives low, the net will be pulled-down to '0'. -------------------------------------------------------------------------------- You can also refer to the open-drain circuit.
Output state wouldn't be set through a weak-pull resistor, this has an effect only for input or bidir pins (also open-drain, of course). weak pull-up can be enabled in Pin Planner tool (with newer Quartus versions) or in assignment editor, also for group of pins with wildcard pingroup* syntax. As nearly everything you may (...)
1) im using the circuit below and when im connecting pull-up or pull down resistor the system not working ! , i know that PORTB in PIC18F4550 has internal resistors but even when i connect resistors to PORTD system in not working as it should be. "Not working" is in fact a vague information. I understand, that the circuit is intende
hi today i tried to build a simple program that turns on LED when a button is push, using weak pull-up feature list F=inhx8m, P=16F688, R=hex, N=0 #include P16F688.INC __config _INTRC_OSC_NOCLKOUT & _WDT_OFF & _PWRTE_ON & _MCLRE_OFF & _CPD_OFF & _BOD_OFF & _IESO_ON & _FCMEN_ON ;definitions --------------------------- ba
I am using PIC18F452 controller, in this i want to use PORTC to interface a compass. In the datasheet he mentioned PORTB has weak pull-up resistors, but he didn't mentioned anywhere about PORTC pull up resistors. Does PORTC have pull ups?
Hi, Prove it to yourself, if you have Mclre ON and leave Pin1 unconnected , the program may not run at all, or run on and off because that pin is floating. For that reason you must tie Pin1 to Vdd either direct or via a resistor, typically 10k, which is often used with a cap in a reset switch situation. I believe the weak internal pull up yo
The datasheet of a 16F877 says weak pullup current 50 to 400 uA at 5V which means the weak pullup can range from 12K5 to 100K. I often use them if I have to connect keys to a pic so I do not need any external resistor to +5V. If you do not enable the weak pullups the pin is floating if (...)
I want to add a weak pull-down resistor on 3-state output buffers and bidirectional buffers in Xilinx FPGA, I have tried to code it like this: IOBUF KIO_0 (.O(KIO_I), .IO(KIO), .I(KIO_O), .T(!we)); IOBUF KIO_1 (.O(KIO_I), .IO(KIO), .I(KIO_O), .T(!we)); IOBUF KIO_2 (.O(KIO_I), .IO(KIO), .I(KIO_O), .T(!we)); IOBU
Hi, I have to place a pull-down resistor on an FPGA output that is HiZ or weak pull-up during start-up. The line is quite long and I wonder if I should connect the pull-down to the driver side or to the receiver side of the signal. Any ideeas or docs on this?
I have read some where that the pull up transistors should be weak...why is it so?
In PIC18F4550, only PORTB has internal weak pull-ups, the other ports don't. Hope this helps. Tahmid.
Port 0 has dynamical push-pull instead. Omitting weak pull-ups apparently seemed appropriate to the original 8051 designers. The detail has been copied with each 8051 compatible IO-port since 30 years. 8051 developers use to know this, or learn it later on.
... and I would add: If the device with x18 /x36 architecture is otherwise suitable, available, and of right price (and you do not need error checking or correction (parity / ECC)), you can use them and leave the extra bits unused. However, you should use for example a weak pull-up or pull-down on those extra data lines to prevent them to (...)
i have another question? what is weak pull-UP? this is also a feature of the PIC controller? can someone explain this feature. thanks If you enable "weak pullup" on PORTB it is like you have connected 8 pullup resistors with a value of about 47K to 250K from PORTB0 ... PORTB7 to +5V. On some (...)
All unused inputs should be tied high or low, a resistor is not needed, all unused outputs can be left floating. This is a rule of thumb for all digital circuits. Not for all - most of modern ICs have internal weak pull-up or pull-down, otherwise it will be pain for PCB designer to place hundreds of resistors
as far as I remember the 8051 has a weak pull-up current source of about 100uA at his ports. It is not able to drive a ULN2803! You will need an external pull-up resistor. The current consumption is to high for more channels. An external FET is only a solution if it is a logic-level FET ! You need a flyback diode. The best way is to use a (...)
Spartan-III have a pin called HSWAP_EN. From the Xilinx doc: A Low on this pin enables weak pull-up resistors on all pins that are not actively involved in the configuration process. A High value disables all pull-ups, allowing the non-configuration pins to float. This is a dedicated pin, and is used for when the FPGA is not yet (...)
At 8051 the ports don't have a "direction" register like other microcontrollers. If you write 1 at the port line it's the same as setting the port as output in high state or set as input (except port 0). The port have a weak pull up that will source current when it's pulled low by a external load like a resistor connected to ground or a (...)
Hi, power-twq I think that you maybe make a mistake. The lib of X1, X2, X3 ... are only for drive ability. In each process lib, there are some pad for weak output, such as pull-up pads and pull-down pads. You can request those datasheet from TSMC or SIMC etc. Good Luck
It can be dangerous for the 89C51. First, the voltage is to high, and second, microcontroller pins are not designed to source that much current, maybe per pin, but not per whole port. Supply this 7-segment of 5V or, using reverse logic use 7 npn transistors to drive the 7-segment display of 12V (with 1kΩ resistors between each transistor and
In the case of the push-pull pad you have strong low and strong high. In the case of the push-up you have strong low and weak high without external resistor or current source. In the case of the open-drain you have strong low and high impedance state. You can use open-drain pad to connect more signals to one common line with active low e
Hi, The AT89S52's ports have a weak pull-up that holds the outputs at 5V when the pin is written with "1". (Port 0 don't even have these pull-ups) This can affect the rise/fall times of the signals due to the cable capacitance and beside that, it makes the transmission susceptible to EM noise. You can try buffering your connection, using (...)
It's possible that you have the outputs configured with weak pull-ups enabled. The i/o's can be configured with weak pull-up, pull-down, or none. weak pull-ups would explain the voltage you see but will not supply enough current to cause the led to emit.
Hi Fuzzzy, I thihg that the Mosfets can be ON during startup. In the schematic picture you can see the reason. When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high impedance input with a weak pull-up 100k to VDD. One solution of this problem is connect resistor betwen Gate Mosfet and VSS. JURS
How have you set up internal pullup: Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The (...)
I need an "interface" so to say, for the PIC pins, though I might use it at something else too. Basically, it should have a led and a button. If the pin is an output, the led should light up depending on the pins state. Pushing the button wouldn't affect it, nor make any problems. If the pin is an input, the button will 'set' a state on the pin
A weak pullup will hold a value on a pin while all other drivers are in tri-state, and can be over-ridden by the value of the driver, once it starts driving. A strong pullup cannot be over-ridden by the driver, and will cause contention.
Many FPGA have unconditionally active weak pull-up resistors, some provide a selection between high impedance and weak pull-up by pin-strapping.
Hi, /***************************************** include // SFR declarations void InitPort() { XBR2 = 0xD8; // Enable crossbar and weak pull-up P2MDOUT |= 0xFF; } void main() { InitPort(); } *****************************************/ i think for enabling crossbar & disabling weak pull-up's (...)
Hi Have you any pull-down resistors on your input pins? The PIC input pins are high impedance and will hold a HI charge for some time. It is common (and good) practice to have the pins inactive HI and then switch them LO to GND/VSS. You can then use the weak pull-up feature built into PortA of the 16F690 and save on hardware. (...)
i want to control DC motor using PIC18f452& transistor TIP120 and i use port B (PB07) to switch on and off but the problem the motor does not run properly i heard that we have to use port C to control motor because portB is weak pull up is it true??
Try to set this RX pin as input (this will put the corresponding output driver in a High-Impedance mode) and maybe disable the weak pull-up .. IanP :D
This is a question of the FPGA hardware features rather than of VHDL syntax. In simulation, all registers are assumed unitialized 'U' on simulation start. In almost any FPGA family, they are initialized at power on, the default state is usually '0' but can be changed by specifying an initial value in the signal definition. Using an initializer is a
Sounds like you are trying to make a 8051 output port source current to the opto coupler. As you can read from the data sheet, they aren't intended for this operation, they are just open drain outputs with a weak pull-up. The most simple method would be to operate the output active low rather than active high. If you ever studied 8051 example cuirc
Hi, I have a design, in which there is a hard macro memory IP block. The data bus of the memory is a tri-statable bus. When the memory goes idle, the bus goes high impedance. To prevent the floating net from causing any power leakage issue to other gates, I did a design like the one in the attach diagram. Basically the NAND gates allow data
Hi, I see that there are a lot of schematics where there are pullups on pins that also have a driver. Can you do this with any signals (i usually see it on reset signals)? How weak has the pullup so the driver can still make the signal 0? Thanks
The purpose of the std_logic resolution function is to handle tristated drivers 'Z' and weak pull-up and pull-down signals. But the example is only involving permanently enabled strong drivers. In so far, there's no room for resolving anything.
Some FPGA power up with a weak pull-up resistor at all I/O pins. If you won't signals turned on before configuration, you should define I/O signals active low. It's also usual, to have higher drive strength for low side transistors, but the ration isn't very high for usual CMOS I/O standards. I don't see a problem to drive moderate LED currents
So can u suggest me any way by which i can send data "FFH" to GLCD without making it an input port?? Just send 0xFF using a typical sequence: MOV A, #0FFh MOV P0, A Sending a ?1? to a port pin does not define whether the pin becomes an output or an input. It activates a weak pull-up inside the microco
Usually SPI doesn't use pullup unless you have a microcontroller that has open drain outputs or very weak current sourcing capability. pullup resistors are used in I2C which uses open drain pins but this is a different case.
Although not used in synthesizable hardware descriptions, 'L' and 'H' can be seen as a representation of hardware features like weak pull-up or pull-down resistors and input hold circuits.
I'm using an FPGA in 2 clock domains. The first clock is a very slow 32KHz - active all the time The second clock 100MHz is inactive when the circuit is in sleep mode - This is done by disabling the "output enable" pin of the clock oscillator. The problem is that when the output of the 100MHz clock is disabled it's high 'Z'. I'm a little re
weak pullup and similar CPLD properties are hardware features that have to be defined in vendor specfic constraint files or configuration tools. It can't be set in generic HDL, may be with vendor specific attributes. I can confirm that Cool Runner II offers weak pull-ups according to data sheet. But I'm not using Xilinx (...)