14 Threads found on edaboard.com: Weak Pullup
If the second application is also digital (I/O, PWM, etc.), then there's no need to remove it. You might need to make it a "weak" pull-up if the alternate function is an output.
Miscellaneous Engineering :: 05-23-2016 07:29 :: spudboy488 :: Replies: 2 :: Views: 461
If you remove the pullup resistor, the microcontroller will stay interrupted all the time. If you have an internal weak pullup it will stay interrupted until the capacitor get a big enough charge so the voltage on the interrupt pin is above the interrupt level.
Not a good idea!
You should connect the pullup resistor to (...)
Microcontrollers :: 11-03-2015 15:33 :: Gorgon :: Replies: 7 :: Views: 489
TTL has a natural pullup and, if the pin is truly open, will
assume a weak (but adequate) "1" state. Of course that
key assumption should not really be relied upon, in the
CMOS inputs tehd to be very high impedance with ESD
clamps roughly balanced, and you have no good idea
where pin voltage will end up unless you do something
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-07-2014 13:23 :: dick_freebird :: Replies: 4 :: Views: 473
Optocouplers are weak and many are one-sided (a single NPN,
bring your own pullup). They can also be undesirably slow if
they are based on a saturating BJT output switch.
Avago makes opto FET gate drivers. You might find -some-
optothingamabob that does the job for your application.
It's just not something that generalizes well.
Power Electronics :: 03-06-2014 21:37 :: dick_freebird :: Replies: 4 :: Views: 517
weak pullup and similar CPLD properties are hardware features that have to be defined in vendor specfic constraint files or configuration tools. It can't be set in generic HDL, may be with vendor specific attributes.
I can confirm that Cool Runner II offers weak pull-ups according to data sheet. But I'm not using Xilinx and can't tell you (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-04-2013 09:27 :: FvM :: Replies: 3 :: Views: 592
Have you installed the appropriate pullup resistor on MCLR?
Vss/GND yes, Vdd no, unless you are powering the board with the PICkit.
Is the PICkit 2 genuine or clone? You may want to use a weak pulldown resistor on PGM, this seems to be particularly important with certain clones.
Also, if applicable, be sure and disable PGM from within th
Microcontrollers :: 06-15-2012 22:30 :: bigdogguru :: Replies: 2 :: Views: 1253
Usually SPI doesn't use pullup unless you have a microcontroller that has open drain outputs or very weak current sourcing capability.
pullup resistors are used in I2C which uses open drain pins but this is a different case.
Microcontrollers :: 03-31-2012 03:23 :: alexan_e :: Replies: 1 :: Views: 722
Hi i am trying to enable IOCB feature in PIC ... i am trying to use interrupt on change on RB 4-5 port .
I have enable the weak pullup feature and that seams to be fine , but the IOCB ports which i am enabling do not seem to change the value .I am using proteus VSM to check the values ..But the IOCB shows 0 .
Microcontrollers :: 01-14-2012 01:27 :: deeplearns :: Replies: 1 :: Views: 1011
Suggest you use active low logic. Output low on any of the 4 outputs and then look for low on the 4 inputs. You WILL need pullup resistors on the 4 inputs, internal weak pullups may be ok if the port has them, would go for external myself 1-10k ok, I tend to use 4K7.
Added after 6 minutes:
Microcontrollers :: 01-21-2010 10:20 :: GrandAlf :: Replies: 20 :: Views: 8081
Port pull ups are can be enabled so if you are using the lines as inputs, you dont need to add external resistors to pull the lines up to Vcc.
You cant have floating inputs, pull ups hold them in a high state. They are weak pull ups, sort of like adding a 220k resistor to the line.
Microcontrollers :: 07-04-2008 18:42 :: btbass :: Replies: 1 :: Views: 1679
How have you set up internal pullup:
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
Hobby Circuits and Small Projects Problems :: 03-08-2007 19:26 :: IanP :: Replies: 5 :: Views: 3698
When FPGA/CPLD is unprogrammed or disable state I/O pins are in Hi-Z, weak Hi (pullup Hi) or Bus-keep state. In that states you can not burn I/O pin.
If chip is with good latchup protection and designed for live insertion, you can insert chip to socket with power on without worry.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-27-2005 21:34 :: Hero :: Replies: 7 :: Views: 1310
i have another question?
what is weak PULL-UP?
this is also a feature of the PIC controller?
can someone explain this feature.
If you enable "weak pullup" on PORTB it is like you have connected 8 pullup resistors with a value of about 47K to 250K from PORTB0 ... PORTB7 to +5V.
On some small PIC's like
Microcontrollers :: 10-28-2004 02:55 :: C-Man :: Replies: 6 :: Views: 2493
The datasheet of a 16F877 says weak pullup current 50 to 400 uA at 5V which means the weak pullup can range from 12K5 to 100K.
I often use them if I have to connect keys to a pic so I do not need any external resistor to +5V.
If you do not enable the weak pullups the pin is floating if (...)
Microcontrollers :: 11-03-2003 00:56 :: C-Man :: Replies: 4 :: Views: 5544