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38 Threads found on edaboard.com: Weak Pullup
The datasheet of a 16F877 says weak pullup current 50 to 400 uA at 5V which means the weak pullup can range from 12K5 to 100K. I often use them if I have to connect keys to a pic so I do not need any external resistor to +5V. If you do not enable the weak pullups the pin is floating if (...)
A weak pullup will hold a value on a pin while all other drivers are in tri-state, and can be over-ridden by the value of the driver, once it starts driving. A strong pullup cannot be over-ridden by the driver, and will cause contention.
Hi hch16550, All four ports 0,1,2,3 of MCS51 are bidirectional. However only port 0 is considered "true" bidirectional, because when configured as an input, it floats. Ports 1,2 and 3 are sometimes called "quasi - bidirectional" due to the fixed internal pullups. You can read a good document about hardware inside standard MCS51 at: http:
i have another question? what is weak PULL-UP? this is also a feature of the PIC controller? can someone explain this feature. thanks If you enable "weak pullup" on PORTB it is like you have connected 8 pullup resistors with a value of about 47K to 250K from PORTB0 ... PORTB7 to +5V. On some small PIC's like
I don't think it is possible to disable the weak pullups on this micro. It is basically an 80C32, where the pullups are always on, to allow the I/O pins to function as both inputs and outputs, simply by clearing the port latch; there is no data direction register. Is it really that important to have the pullup disabled? (...)
Hi, Like Davood Amerion says, you can use most any pins of the CPU. BUT, if you choose ones with an internal weak pullup (and enable those weak pullups), you'd require 2 components less, and make your PCB that much simpler. Regards, Anand Dhuru
now the problem has been fixed by adding option of 'weakgate' when 'run build_model' . the pad cell has weak pullup or pulldown, which TetraMax regards as contention. hope to be helpfull to others.
Tristate logic can cause power waste. adding a weak pullup or pull down to the net would remove the power waste
When the I/O pin has no connect, which one is better for port output mode as following: 1. Quasi-Bidirectional 2. Push-Pull 3. Input Only (High Impedance) 4. Open Drain I have read from "P89LPC9221 User's Manual" as following: Quasi-bidirectional output mode, 'One of these pull-ups, called the 'very weak' pull-up, is turned on wheneve
It would be helpful to see all the source code, if it's not confidential. In your simulator display, be sure you aren't confusing the floating 'z' state with the unknown 'x' state. Signal contention (two drivers fighting with each other) can result in an 'x' state. By the way, your test bench is not simulating the open-drain nature of I2C. It
Port pull ups are can be enabled so if you are using the lines as inputs, you dont need to add external resistors to pull the lines up to Vcc. You cant have floating inputs, pull ups hold them in a high state. They are weak pull ups, sort of like adding a 220k resistor to the line.
Wanting to use MCLR as interrupt port change state - its set high. Prefer to use weak internal pull-up. Tried this: ioc.3=1; intcon.GPIE=1; //enable IOC bit for GP3, then GPIE //in ISR checked for state when button pressed high to low thusly: if (GPIE && intcon.GPIF) //nosuch IRQ not being called The logical port to use would be GP2/ext int p
Here is a job: To sense ambient light change as a switch from say day to night, with eg PIC10F206. Device between input port with weak pullup enabled, and VSS. Possibly use the comparator for validity of change and hysteresis. Assume LDR is the better of the two options or is there another device to consider mainly need lowest cost part thanks v
Hi Silver, From your description it looks like you need a range of just a few cms between the IR source and the detector. If you shield and align both properly, you should get away with directly connecting the IR receiver diode to the PIC's input; use a pull-up from this point to +5v. When the receiver sees IR, the port pin will drop to 0. Choos
it appears that you are driving the data line high during the read I don't think so. The code seems to be dedicated to 8051 standard IO. It has open drain ports with weak pullup, without any data direction register. There's no risk of driving SDA high with these interfaces.
hi i need code which generate ir 38 khz pwm using pic12f675You do not normally need PWM for 38KHz IR, just square waves. This should do it: ;IRTX - use MPASM in relocatable mode #include p12f675.inc ;with analogue __CONFIG 0x0184 errorlevel -302 ;prevent bank select warnings #define irou
Hi i am trying to enable IOCB feature in PIC ... i am trying to use interrupt on change on RB 4-5 port . I have enable the weak pullup feature and that seams to be fine , but the IOCB ports which i am enabling do not seem to change the value .I am using proteus VSM to check the values ..But the IOCB shows 0 .
weak pullup and similar CPLD properties are hardware features that have to be defined in vendor specfic constraint files or configuration tools. It can't be set in generic HDL, may be with vendor specific attributes. I can confirm that Cool Runner II offers weak pull-ups according to data sheet. But I'm not using Xilinx and can't tell you (...)
Hi endikus, your schematic is OK as far as I can see. You must use pullup resistors to +5V (4K7) at each output of your 89C52 which is driving the ULN. The internal pullups of 8051 are too weak to fully switch on your ULN. hope this helps, best regards
Hi, When FPGA/CPLD is unprogrammed or disable state I/O pins are in Hi-Z, weak Hi (pullup Hi) or Bus-keep state. In that states you can not burn I/O pin. If chip is with good latchup protection and designed for live insertion, you can insert chip to socket with power on without worry.
You didn't say which FPGA or how the input is configured. If the input pin is used internally, then the typical FPGA input is very high impedance, so the signal will float. You breathe on it and it will probably change state. It may pick up noise or consume extra power too. Some FPGAs provide configurable pullup or pulldown resistors on input pins.
:idea: : I consider a :arrow: tristate input x :arrow: tristate output e :arrow: tristate enable (active high) gate U1, U2 and U3 U1(a) connected to '0' U1(e) connected to first input U1(x) connected to U3(e) + pullup U2(a) connected to '0' U2(e) connected to second input U2(x) connected to U3(a) + pullup U3(x) connected to a
I want to add a weak pull-down resistor on 3-state output buffers and bidirectional buffers in Xilinx FPGA, I have tried to code it like this: IOBUF KIO_0 (.O(KIO_I), .IO(KIO), .I(KIO_O), .T(!we)); IOBUF KIO_1 (.O(KIO_I), .IO(KIO), .I(KIO_O), .T(!we)); IOBUF KIO_2 (.O(KIO_I), .IO(KIO), .I(KIO_O), .T(!we)); IOBU
No. The pull-up resistor only acts as a "weak" pull-up source. So when slave drives low, the net will be pulled-down to '0'. -------------------------------------------------------------------------------- You can also refer to the open-drain circuit.
The output of 8051 (both C51 and S51) is not a push-pull type output. It is a weakly pulled-up open-drain type output. It can sink large currents (5ma or so) but can source only a few micro-amps. So if you feel that the output is not capable of driving properly, you connect about 4.7kohm resistors between the port pins and +5V. Alternately, you c
How have you set up internal pullup: Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
The receiver probably contains garbage from when the RS-485 receiver when from the previous enable to disabled. I would flush the UART receive buffer BEFORE re-enabling the RS-485 receiver. I am not familiar with how to do that on a PIC, on an AVR, I just read the buffer register and discard the result. How long are your interconnect cables?
Hi. I have a doubt regarding VHDL 9 value logic application in Xilinx FPGA. Its is said that there are 9- logic values which can be used while writing HDL's but in most of the designs i can see obly logic 0, logic 1 and 'Z' (High Impedence). I am writing a code for Spartan FPGA's. My question is, what is the use of weak Unknown(W
May be this one is already out of date but for what its worth. As Bobi said, The inputs of the LPC2129 can tolerate 5V. What you could do is to connect a pull-up to the port pin, connecting it with 5V. If you drive the pin low, the max 4mA of the port pin have to be strong enough to get to low-level. If you want to have a high-level, you put the p
i still cound find out the answer!!!! thxs for helping OK first, are you sure your logic is correct? Your initial logic seems to be waiting for a high, then timing a high pulse. Most modules output low, so a start bit is a low pulse not high.. Of course you could have an inverter or different module, but it's the fir
PORTB has built in weak pullups, you have to enable them RBPU Connect one side of your DIP switch to GND
Hi, are there any pins that need to go to a high state after reset? If so, the internal pullup after reset is VERY weak and often can not pull a pin high. You need toi use external pullpus in such a case or you switch the portpin to low and then to high, much stronger pullups are involved in this action. Just a guess because I have seen (...)
Suggest you use active low logic. Output low on any of the 4 outputs and then look for low on the 4 inputs. You WILL need pullup resistors on the 4 inputs, internal weak pullups may be ok if the port has them, would go for external myself 1-10k ok, I tend to use 4K7. Added after 6 minutes: Simulation give
All P1 port pins have “weak” internal pull-ups, so if you use them as general purpose input/output pins you don’t need to add any external pull-up resistors .. Rgds, IanP :|
Look at your driver spec VOL condition, usually milliamps of load. Below this it's guaranteed to make VOL. You may not need to pull that much. It wastes power. pullups can help deal with things like what happens to that "output" signal (your input) during power-up where FETs might be too weak to assert a proper state, the pin goes intermitten
Usually SPI doesn't use pullup unless you have a microcontroller that has open drain outputs or very weak current sourcing capability. pullup resistors are used in I2C which uses open drain pins but this is a different case.
Have you installed the appropriate pullup resistor on MCLR? Vss/GND yes, Vdd no, unless you are powering the board with the PICkit. Is the PICkit 2 genuine or clone? You may want to use a weak pulldown resistor on PGM, this seems to be particularly important with certain clones. Also, if applicable, be sure and disable PGM from within th
Your BC558+ SW + 26K config is very unusual. What are you trying to do here ? I suspect this needs to be improved - especially when the Switch is open & your base floats. Also imho your MCLR should be pulled to Vcc, even though it already has a (weak) internal pullup An open pin can pick up noise easily and cause problems. Also in general yo