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4 Threads found on edaboard.com: What Is Mirror Pole
I find myself curious about this circuit. I think I am missing something because it appears to me that Q1 and Q3 counteract each other, with Q6 countering the current influence of Q3, If Q3,Q4,Q5,Q6 equal in size, then they all cancel the push/pulling of current from each other, meaning just Q1 and Q2 determine Vo. I do not see the point of this. I
Analog IC Design and Layout :: 02-04-2013 15:36 :: prestonee :: Replies: 21 :: Views: 1165
dear every body
could you pls tell me what is the physical meaning of the mirror pole and rezo ?
many thanks in advance
Analog Circuit Design :: 06-29-2012 06:49 :: dinosaur078 :: Replies: 0 :: Views: 735
This is bias circuit. what's the advantage of this tpye? Thanks
Analog Circuit Design :: 11-23-2008 20:01 :: qwertyIC :: Replies: 4 :: Views: 834
(1) what is the relation between phase margin and settling time? From rajavi (page 354), I can concldue that better the phase margin, slower is the response or settling time is more. Correct me if I am wrong!
(2) Now if we are talking about pole-zero doublet, we should specify whether it is right half or left half plane zero. In
Analog Circuit Design :: 07-05-2006 07:01 :: pixel :: Replies: 12 :: Views: 9712