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23 Threads found on edaboard.com: What Is Mirror Pole
dear every body could you pls tell me what is the physical meaning of the mirror pole and rezo ? many thanks in advance
(1) what is the relation between phase margin and settling time? From rajavi (page 354), I can concldue that better the phase margin, slower is the response or settling time is more. Correct me if I am wrong! (2) Now if we are talking about pole-zero doublet, we should specify whether it is right half or left half plane zero. In
The purpose of my suggestion was for you mainly to test the normal current mirror operation in your simulator. Have you tested it?? I agree with cellphone, that is also what I guessed: the diff. transistor pair do not get correct DC bias from V3! To check this, omit V3 and bias base 5 and base 6 via two separate resistors from V1, ok?
Hello reg_ic, hr_razaee, I do not understand how the the freq. resp of one is better than the other. First order, your BW is determined by gm6 and the output cap that is present on the drain of M6 and M7. And, the gm of M6 is the same in config1 and config2. Could you please explain to me and tell me what I am missing?[/q
can you tell me the differences between "the basic differential pair" and "the differential with active current mirror" ? i know the latter increases a "mirror pole", i.e., it has worse stability. what are the other advantages and disadvantages of the two circuits ? plz help me, thanks in advance. jeffrey
Hi Junus, finally, I don`t know what your problem is. Please, explain in detail. Let me summarize: 1.) You have a circuit (without internal pos. feedback) with certain gain and phase characteristic. Gain is approx. 70 dB. 2.) Resulting from internal pos. feedback the gain is somewhat increased and the phase is enhanced. This gives an improved pha
Here are few question Gain, (how to improve gain?) Bandwidth, (how to improve bandwidth?) Feedback,(Stability is a must ask question! Know pole, zero, gain and phase margin!) Slew rate,(How to improve slew rate?) Offset,(how to eliminate offset? Chopper stabilized circuits, autozero) Noise,(what is thermal, flick, shot noise? (...)
most effective is to mirror the power pmos while not connecting the drain together. arsenal what is the meaning, may you explain in detail, thanks!
while designing opamp for first order bandgap,what are the specifications of the opamp we should keep in mind other than high gain.
what is your speci ?? 1. High speed -> BW > 300M or 1G ? 2. low power --> current < 1m or 100ua ? BamdWidth > 100M , I think should called video amplifier not OPA by the way , have anyone design CMOS Current Feedback Amplifier ?? how to reduce input offset ?
Hi, 1) First, what is the intent of your main circuit? You have the input at gate of NMOS differential pair tied to gate of an NMOS load (positive feedback?) 2) You have shorted the output with a resistor (Why?). 3) For stability analysis, you have to keep Rc in place - the second picture shows that one of the Rc is missing. 4) In your
what is the mean of mirror amplifier ? thanks!
For the cascode transistors they need to match their Vgs so their W/L should be large, at the same time their ro should be large so as to make the fold node look like a low impedance towards them and most of the small signal current goes through them. The trande off is the noise performace. why ro is large that make the f
note that what u need to compensate is the CMFB loop not the CMFB amplifier and as u say by increasing the load capacitance u push the dominant pole to roll-off earlier and the dominant pole of the differential amplifier is at the same time the dominant pole of the CMFB loop(assuming that the mirror (...)
hello, With 2 uF( quite large ) output capacitor, I think your dominant pole will be in output (Vo) anyhow no matter what is the load condition. The compensation scheme you showed is cascode compensation, aspired by Ahjua more than 20 year ago. It kills the feedford path while keep the feedback, so the miller effect remains.
what are the advantages of current mirror OTA ? Could it be considered a good topology for LDO error amplifier -at least as a first stage-(I have saw it in some papers but without reasoning for its usage)? what I know is that it has a larger output swing & 1 pole-& the other is at high frequencies- (although composed of 2 stages
This is bias circuit. what's the advantage of this tpye? Thanks
Hi, I am running a pole zero analysis via cadence spectre on a two stage opamp which consists of the classical diff pair with current mirror load and as second stage the classical common source/inverter problem is that i cannot see the RHP zero that is created via the feedforward path of the miller compensation capacitor...All t
Thanks for the information, i shall go research on what you all had mention
Hi dedalus, Thank you for your post. Actually the drain of the pmos input stage IS (not ARE) connected to the nodes between drains and sources of the BOTTOM nmos cascode. The first stage has its own current mirror load. It's two stages for sure. From what you say, it looks like a folded cascode topology. Put in sim
Hello, I have designed a fully differential Miller OpAMP with CMFB. I need it to create a library of elementary filtering stages (first order LP and HP, second order LP, HP and BP, the biquad topologies etc).The amplifier appears to work well. in an amplifier connection and in lowpass. However, for highpass and bandpass the CMFB doesn't work and
SIR, im designing an OTA telescopic wid certain gain enchancement modification architecture wid current mirror technique .018 technology... i got my gain enchanced by 6 db bt my phase margin got very much decreased to 54 from 78.... what shud i do to bring pm to more than 60 ...i took currents as 200uA for the ota...suggest
Hi LvW what do i do to improve phase margine of my opamp.......?? As the simplest method try to reduce the first pole frequency from app. 100 kHz to e.g. 10 kHz (or less).