23 Threads found on edaboard.com: What Is Mirror Pole
dear every body
could you pls tell me what is the physical meaning of the mirror pole and rezo ?
many thanks in advance
Analog Circuit Design :: 29.06.2012 06:49 :: dinosaur078 :: Replies: 0 :: Views: 470
(1) what is the relation between phase margin and settling time? From rajavi (page 354), I can concldue that better the phase margin, slower is the response or settling time is more. Correct me if I am wrong!
(2) Now if we are talking about pole-zero doublet, we should specify whether it is right half or left half plane zero. In
Analog Circuit Design :: 05.07.2006 07:01 :: pixel :: Replies: 12 :: Views: 8535
The purpose of my suggestion was for you mainly to test the normal current mirror operation in your simulator. Have you tested it??
I agree with cellphone, that is also what I guessed: the diff. transistor pair do not get correct DC bias from V3! To check this, omit V3 and bias base 5 and base 6 via two separate resistors from V1, ok?
Analog Circuit Design :: 12.01.2007 18:50 :: unkarc :: Replies: 15 :: Views: 759
i have two choice of the amp ,but i cant make understand what is the different between them ! pls give me some advice and thx advance!
from the view of amp gain i think they are the same, but if you meet these two amps ,which will you choose and why ?
Analog Circuit Design :: 10.08.2007 11:12 :: reg_ic :: Replies: 12 :: Views: 1250
can you tell me the differences between "the basic differential pair" and "the differential with active current mirror" ?
i know the latter increases a "mirror pole", i.e., it has worse stability.
what are the other advantages and disadvantages of the two circuits ?
plz help me, thanks in advance.
Analog IC Design and Layout :: 29.01.2011 23:10 :: sevid :: Replies: 9 :: Views: 1906
I find myself curious about this circuit. I think I am missing something because it appears to me that Q1 and Q3 counteract each other, with Q6 countering the current influence of Q3, If Q3,Q4,Q5,Q6 equal in size, then they all cancel the push/pulling of current from each other, meaning just Q1 and Q2 determine Vo. I do not see the point of this. I
Analog IC Design and Layout :: 04.02.2013 15:36 :: prestonee :: Replies: 21 :: Views: 725
Here are few question
Gain, (how to improve gain?)
Bandwidth, (how to improve bandwidth?)
Feedback,(Stability is a must ask question! Know pole, zero, gain and phase margin!)
Slew rate,(How to improve slew rate?)
Offset,(how to eliminate offset? Chopper stabilized circuits, autozero)
Noise,(what is thermal, flick, shot noise? (...)
Analog Circuit Design :: 18.08.2004 04:11 :: gold_kiss :: Replies: 19 :: Views: 3822
most effective is to mirror the power pmos while not connecting the drain together.
what is the meaning, may you explain in detail, thanks!
Analog Circuit Design :: 19.05.2007 09:06 :: mists :: Replies: 32 :: Views: 8054
while designing opamp for first order bandgap,what are the specifications of the opamp we should keep in mind other than high gain.
Analog Circuit Design :: 25.02.2005 03:56 :: avinash :: Replies: 25 :: Views: 2834
what is your speci ??
1. High speed -> BW > 300M or 1G ?
2. low power --> current < 1m or 100ua ?
BamdWidth > 100M , I think should called video amplifier not OPA
by the way , have anyone design CMOS Current Feedback Amplifier ?? how to reduce input offset ?
Analog IC Design and Layout :: 14.07.2005 05:15 :: andy2000a :: Replies: 13 :: Views: 1795
1) First, what is the intent of your main circuit? You have the input at gate of NMOS differential pair tied to gate of an NMOS load (positive feedback?)
2) You have shorted the output with a resistor (Why?).
3) For stability analysis, you have to keep Rc in place - the second picture shows that one of the Rc is missing.
4) In your
Analog Circuit Design :: 16.05.2006 08:13 :: tsb_nph :: Replies: 11 :: Views: 2197
what is the mean of mirror amplifier ? thanks!
Analog Circuit Design :: 04.12.2006 08:10 :: mists :: Replies: 16 :: Views: 1304
I think you meant that your MAXIMUM power dissipation spec is 0.75mW. For a 5MHz GBW with a 5pF load you need a gm of at least 25uS, this is assuming that your input transistors are not so big so as to make the input pole closer. So you need to decide a limit on the size of the input transistors based on the driving impedance of the source and then
Analog IC Design and Layout :: 12.11.2006 01:28 :: aryajur :: Replies: 20 :: Views: 1949
note that what u need to compensate is the CMFB loop not the CMFB amplifier and as u say by increasing the load capacitance u push the dominant pole to roll-off earlier and the dominant pole of the differential amplifier is at the same time the dominant pole of the CMFB loop(assuming that the mirror (...)
Analog Circuit Design :: 14.12.2006 05:01 :: MSSN :: Replies: 3 :: Views: 1177
Hi ,everyone :
I have one question :
The upload shcematic is a LDO . It uses the Miller compensation
as the upload paper using current buffer(T1 and C4) ?
In the shcematic uploaded , all cap is several pF , except the Cl ,which is
at least 2uF ( the datasheet specify " For stability , it must be at least 2uF) .
My question is
Analog Circuit Design :: 23.04.2007 10:17 :: fanrong :: Replies: 6 :: Views: 1753
what are the advantages of current mirror OTA ?
Could it be considered a good topology for LDO error amplifier -at least as a first stage-(I have saw it in some papers but without reasoning for its usage)?
what I know is that it has a larger output swing & 1 pole-& the other is at high frequencies- (although composed of 2 (...)
Analog Circuit Design :: 17.05.2008 17:25 :: quaternion :: Replies: 15 :: Views: 3399
This is bias circuit. what's the advantage of this tpye? Thanks
Analog Circuit Design :: 23.11.2008 20:01 :: qwertyIC :: Replies: 4 :: Views: 705
I am running a pole zero analysis via cadence spectre on a two stage opamp which consists of the classical diff pair with current mirror load and as second stage the classical common source/inverter problem is that i cannot see the RHP zero that is created via the feedforward path of the miller compensation capacitor...All t
Analog IC Design and Layout :: 26.05.2010 11:33 :: jimito13 :: Replies: 0 :: Views: 1193
Thanks for the information, i shall go research on what you all had mention
Analog Circuit Design :: 05.06.2009 21:07 :: Hitotsu :: Replies: 4 :: Views: 1015
Thank you for your post. Actually the drain of the pmos input stage IS (not ARE) connected to the nodes between drains and sources of the BOTTOM nmos cascode. The first stage has its own current mirror load. It's two stages for sure.
From what you say, it looks like a folded cascode topology. Put in sim
Analog Circuit Design :: 23.05.2010 09:13 :: amriths04 :: Replies: 7 :: Views: 1273
... My guess is that because of the longitudinal capacitance, the common mode Vref voltage doesn't reach the OpAMP input (in DC). what could the solution be to my problem?
Use an additional parallel DC path, s. the foll. PDF: 49211
And I think the paper from Jian Xu et al. "Low Voltage Low Power C
Analog IC Design and Layout :: 13.09.2010 11:11 :: erikl :: Replies: 7 :: Views: 972
im designing an OTA telescopic wid certain gain enchancement modification architecture wid current mirror technique .018 technology...
i got my gain enchanced by 6 db bt my phase margin got very much decreased to 54 from 78.... what shud i do to bring pm to more than 60 ...i took currents as 200uA for the ota...suggest
Analog Circuit Design :: 26.06.2011 08:01 :: satyanitt :: Replies: 4 :: Views: 618
what do i do to improve phase margine of my opamp.......??
As the simplest method try to reduce the first pole frequency from app. 100 kHz to e.g. 10 kHz (or less).
Analog Circuit Design :: 25.08.2011 09:06 :: LvW :: Replies: 4 :: Views: 461