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67 Threads found on Width Verilog
Hi I disgned 128b/132b encoder and decoder block in verilog code but my data width is 8 bit and my encoder' s input in 128 bit so how can I communicate my data bus with encoder?how can this encoder get 16 8 bit symbol?
I am very new to functions, I have a parameter to specify the input freq(mhz). Would this return a value I could use to specify a vector width? function int _ms_unit_width; int freq_mhz = (int_input_freq_mhz/1000); _ms_unit_width = ($clog2(freq_mhz)+1); endfunction
Can you help me understanding this my_ByteSel = {8?d3, 8?d3} width = 8 my_pointer (value) `width * (value) +: `width Wire my_counter; this is what I would like to understand --> my_counter(my_ByteSel) assume that value will take  0 and 1 ? only two values. Thanks..
But the error still exists with the following operation mem_addr*MEM_DATA_widthYour snippet compiles correctly when changed to indexed part select.
Hi All, I am using verilog A model ofTFET from Penn State University which is given below. `include "constants.vams" `include "disciplines.vams" module NTFET(d,g,s); inout d,g,s; electrical g,d,s; real Ids, Cgs, Cgd, Qs, Qd,Qg; parameter real W=1; //Device width analog begin Ids=$table_model(V(d,s), (V(g,s)), "IdVg-NTFE
verilog requires that slices of bit vectors have constant width. Even though you could prove the range of your simple case has a constant width of 10, verilog does not allow that syntax. Use the +: range construct. See
assign some_signal = ~0; also works when you do not have a width parameter avail.
You have to instantiate the alu module inside the ralu module if you want to have the op1, op2, func, and out to connect to anything in ralu. Right now you have two separate modules with no connections between them. You should fix the width of func, it's defined as 4-bit but should only be 3-bits. Add a default to the
I have a signal with 10 bit width. I want to assign do an operation while this 10 bit signal changes. Can anybody please let me know the synthesizable construct to indicate that whenver this signal 9:0 width changes , an operation can be done? Let the signal name be is high_volt. Whenever high_volt changes I need to do an addition of two o
I have an sram memory . it's data width , address bus width and depth all are sram depth is d and the address bus width must be log2(d) and represented by c parameter . I import the math function library by several methodes in my code but neither of them worked and there were errors. I don't know how to write the width of (...)
Hi all, How we can use the parameter as bit width in verilog for a CONSTANT value representation. For example : parameter VAL = 11; always @ ( posedge CLK or negedge RESETn ) begin if ( !RESETn ) begin count <= {VAL{1'b0}}; end else begin if ( count == 11'h5FF[/C
//RTL version module shiftReg( clk, rst, load, // enable load pIn bus contents into the register sen, // shift enable pin, sout // serial out ); parameter width = 4; parameter hi = 1'b1, lo = 1'b0; input clk, rst; input load; input sen; input pin; output sout; reg sreg; assign sout = sreg[
Hi, this is range definition. Previously defined parameter NUM_CLK_DOMAIN equals to width of VALID_CLK_DOMAIN parameter. If range is not defined, it would be 32 bits. {NUM_CLK_DOMAIN{1'b1}} here replication of concatenation is used. Let's say NUM_CLK_DOMAIN is 8, then VALID_CLK_DOMAIN parameter will be 8 bits wide, and will g
Form system verilog LRM 3.1a, Systemverilog adds the ability to specify unsized literal single bit values with a preceding apostrophe ( ? ), but without the base specifier. All bits of the unsized value are set to the value of the specified bit. In a self-determined context these literals have a width of 1 bit, and the value is treated (...)
Hi, I have the following system verilog code to be compiled in VCS. module (....); ..... ...... parameter width = 8; parameter = {8'h00, 8'hff, 8'h24} ; .... .. endmodule How can i parameterise the size of literals inside the concatenation? so that even if width changes i need not bother about changing the size m
Hello every one. I have same problem about below tx code. Here is a verilog uart transmit code. Here I can send only one character to computer via rs232. In below code can send only 'X' char. I need to send word by word to computer. Please help. module TX (
I have frame width of 64 * 64 pixels. each pixel width is 8 bits. Help me in writing verilog code for the frame.
Hi! I think the most easy way to do so is to write your own preprocessing script to generate the code you want according to some input parameter (in your case the data width). Since the code you are going to generate is very simple you won't have problems in writing a simple script. Then, invoke the script along the flow before going to synthesis.
Hi, If there are 3 single pulse signals, one of which (1st) follow 2nd signal with a delay 10ns, how to compare the other one(3rd) width with the delay value? If 3rd width equals that delay value, indicate it. Thanks.
have you checked whether A and Y is 1 bit width or 3 bit width?
Assume we have an external clock, how I generate pulses that may have a 60 sec period and very small pulse width say 1sec, using a verilog coding (not necessary 1/60 but could be any long period of seconds and a short pulse with) So your frequency is 0.0167 Hz and your "very small pulse width" is a humongous 1,
WIRE if these are individual signals. REG with a width if these are bits of a same bus
Hi all, I have coded a parameterized module in verilog. In this module, one particular parameter configuration leads to an illegal port width which looks like this: reg my_data; and I was surprised to find that VCS didn't flag any error or warning for this. :shock: Functionally, the design is still working fine because in this part
Hi, For an assignment I have to build a variable bit width ALU. I have built all of the modules (adding, subtracting, and, or, xor, etc...) but have built them all hardcoded to 32 bits. for example: my 32bit xor-er `define D 0 module xor32( output C, input A, input B ); //xor all the bits xor_gate #
Pipereg is a parameterized module. The #(1) construct sets the value of the parameter inside pipereg to 1 when it is instantiated. Not having seen the guts of pipereg, we don't know that the #(1) sets a delay. It might set the width of pipereg rather than the depth. If pipereg has only one parameter to set, then typing #(x,y) will at best
Please see this kink. It might help: VHDL, verilog, design, verification, scripts, ... "This projects implements an eight point Decimation In Time Fast Fourier Transform. The internal data buses width and representation will be discussed and explained FFT desig
dear all, iam looking for a verilog code : in which the input control signal is a signal with pulse width of 1us and period of 10us, output signal should be logic 1 when control is zero and 40MHz clock when control signal is logic1 and clk should be assigned after 12.5ns of logic1 . attached figure : module(clk,control,latch_en); input cl
Designing a 5th order filter with only 8 bit data width seems pretty meaningless, but may be O.K. as an exercise. Assuming you want to keep at least the 8 bit resolution in the filter output most likely implies higher internal resolution and possibly higher coefficients resolution. In any case, it's more a DSP numerical than particularly a Veril
Hi guys, I'm a noob trying to become more and more expert ;) The project I'm trying to design should be able to correlate (or auto-correlate) a binary signal (i.e. an arbitrary binary sequence) and output the correlation coeffs using a 16-bit word. All was coded under verilog and I'm using Xilinx Spartan-6 as development board to run it. S
FYI "defparam" is synthesizable. Will be interesting to know which synthesis tool is not supporting "defparam" construct. For your scenario, you can implement like this : mux #(.width(4)) mux_1(.sel(sel0),.a(a0),.b(b0),z(z0)); mux #(.width(8)) mux_2(.sel(sel1),.a(a1),.b(b1),z(z1)); module mux(sel,a,b,z); input [width-1
Dear All, I had written verilog HDL behavioral code for 4 bit 2x1 mux but my requirement is that i want a generalized code so that i can call it from top level module based upon width of my data. I want that mux code to behave as 4-bit wide 2X1 mux or on requirement 8-bit wide 2x1 mux as well in same design.Any suggestion how can i ad
Hello everyone I have a question regarding constant assigments with parameterized bit width. For example, i want to initialize a register with a constant value 10 . If i wish to use a fixed bit width all I have to do is: reg whatever; always @(posedge) begin whatever <= 8'd10; end Now, if I want to define the registers wit
Hi all, I have a rookie question. I did the following code: module adder #(parameter width=8) .... for(i=0;iwidth);i=i+1) ..... function integer log2; input value; for(log2 = 0; value > 1; log2 = log2 + 1) value = value >> 1; endfunction endmodule I get the following
Hello forum users, I'm new in your forum and at first i want to say "hello" :-) I have a simulated testbench with verilog timing checks. The problem is, that no violation come on the $width check. The condition of $width is correct. (threshold < time(opposite_event) - time(reference_event) < limit) In one case, it is so, that the (...)
I have recently run across this verilog coding standard: Use explicit bus widths during assignments, connections, and reads: reg data; always @ ... data <= ... case (state) ... mod mod_inst ( .d(data), ... ); I have serious issues with this, but I'm curious what others think. Thanx, Nachum
Hi, As far as I see, your code is correct. However your secret_number module uses verilog-2001 ANSI style for the ports. Maybe Synopsys Design Compiler does not support this. You could rewrite it to: module secret_number(WE, QE); parameter width = 5; input WE; output QE; endmodule Maybe this solves
i'm developing a function coverage for an exist design module module_m. some input of module_m is defined by parameters. my function coverage should also use the parameters to define the input port. so, the problem is: how can i get the right value from the design file and pass it to my file? the limi
Unlike verilog, vhdl is strongly typed, so you can't implicitly define the length of "a" by its assignment. Assuming signal "a" is a vector of defined width sig_width+1 in its declaration then .... signal a : std_logic_vector(sig_width downto 0); .... begin .... a <= (others => '1'); .... "others" applies to all (...)
Hi all my paralell output signal frequency is 48khz, its width is 24 bits. it has to be converted into serial signal. what my question is how to design a paralell to serial module with verilog. Maybe I can realize it with FSM or a sinple shift-register. which one is better. and the frequency of the serial signal is 48k*24 Hz? a
Model a memory with synchoronous read and write operations that meet the following specifications. -The memory has an address bus width of ADDR_SIZE -The memory has a bidirectional data bus with the width DATA_SIZE. -The memory chip is enabled using an enable signal.When the chip is disabled ,the data bus should be freed. -A single signal tha
Hello everyone, I have a certain number of times data, lets say ten values between 0 and 200 us, and I want to emit a pulse (fixed amplitude, fixed width) at each of these times. For example a pulse will be emitted at 10 us, 54 us, 100 us ... I stored the time values in an array in verilogA, but I dont know how to emit the pulses. Can somebod
yes.. u r right... by defauls a reg or wire are 1 bit unless u mention the bit width as stated earlier... haneet
Hi, I would do it with assiging the each of the index to a wire of 8-bit width and then passing the combined as o/p " wire input ; wire tmp1,tmp2,tmp3; wire tmp; assign tmp1 = input; assign tmp2 = input; assign tmp3 = input; assign tmp = {tmp3,tmp2,tmp1} and during instantiation you can split tmp
because some IP clock width check value in SDF is wrong, so can i turn off these IP width check when SDF annotation? we can not hack the IP verilog library now... and we are running it with NCsim. Thanks
Hi folks Can I change the direction of an already declared bit vector in verilog ? .. Here is an example of what I want to do: wire x; wire y1; wire y2; assign y1 = x; assign y2 = x; ( I want to ask about 'y2' assignment). In VHDL, this is definitely al
Hi, I am converting a VHDL code into verilog. I have a procedure in VHDL. The input argument passed to this procedure has different width at different time. Say for example some time I pass 8 bit vector and some time I may pass 16 bit vector. Inside the procedure they are using 'left and 'right for manipulation. I know task is equivalent to
To my knowledge, it doesn't support two dimensional ports. Its possible to declare ports only as vectors, where the size defines the width of the data bus. I hope that you are referring to the width and depth as two dimensions of the input/output ports.
Hi, this peice of code i got from net... verilog algorithmic level model module GCD_ALG; parameter width = 8; reg A_in, B_in, A, B, Y, Y_Ref; reg A_reg,B_reg,Swap; parameter GCD_tests = 6; integer N, M; reg Passed, FailTime; integer SimResults; // Declare memory array for test data // --------------
now I need a 8byte ~80 byte width CRC32 logic and who can help me the generate script or verilog hdl code for crc32 and thank you!
verilog is best due to simpler learning curve. Plus there are more help in verilog than VHDL. Plus, with IIR you had better stay in DSP processor since in FPGA, bit-width is fixed and IIR is a route to overflow.