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Worst Case Calculation

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14 Threads found on edaboard.com: Worst Case Calculation
You are asking a lot of totally different questions. 1) The input impedance of your ADC has to be much greater than 13k (the impedance of your resistor string), or it WILL affect your reading. That's just a simple parallel resistance calculation. I would buffer it with an opamp. 2) worst case error will be about 1.9%. Assume all (...)
The sensitivity of any formula to a parameter is it's partial derivative. - therefore use mean & % tolerances for linear analysis So Vin = 6~17=11.5 +/- 5.5=11.5 +/- ~50% for sensitivity summations Or use both worst case values ...
I will not trust online tools for optimization...Only basic component calculation and any compensation components calculation ( purely based on personal experience) will be best calculated by online tools ....Human intelligence is required and mandatory......Try to calculate the worst case current(Ripple and peak - mainly (...)
I have designed a 16-bit modified radix-4 booth multiplier in cadence and simulated it using ADE (Analog Design Environment). I wonder if there is any automatic method to calculate the worst case propagation delay of this circuit or I have to use a brute force method to find it? As a matter of fact I don't have enough time to measure the delay of
Depending on the input pattern, one or both paths from input to output can get excited. For example, if B input stays at 1, and A input change from 0 to 1, then Z changes from 0 to 1. In this case the A to Z path is chosen. If both A and B change from 0 to 1, then both paths are chosen and i think the worst path (please double check this) from inpu
you could use the worst case peak current per rail : Ipeak = Pmax / VDD you can estimate the transient current (rule of thumb : Itransient ~ 0.5 * Imax)
Hi All, My small consulting company is moving into an industrial location since we are getting a used CNC milling machine. The machine takes 208V 3-Phase power, and the required current rating is 40 amps. I know that actual current usage depends on the load, but I'm trying to estimate the worst case scenario for the power usage of the machine.
The size of your capacitor will be dependent on full or half wave bridge, worst case load and allowable ripple. As to limiting inrush current either a SCR bridge or diode bridge is used in conjunction to a current limiting resistor with a bypass, the bypass being energised when the voltage has stabilised to within 20% of full voltage. By limiting t
Hi everyone, The foundry usually will provide 3 libraries for synthesis: best case, worst case and typical case. Which one should I use for DC synthesis? Besdies, in generating sdf, which librrary should be used also? Thanks a lot Tonyson
Hi, thank you for replying. I want to do a hand calculation of the NAND3 gate. I wish I can have the instantaneous, average as well as worst case power consumption. I also want to take the charge sharing effect into consideration. The transistor we use is nano scale transistor, so I doubt I can not use the square law of current equation (...)
Here's some thoughts: 1) You need to look for worst case transitions. In a NOR gate, to switch low, worst case is only ONE nmos device pulling low (not two), hence one signal should stay low (while the other rises). If you keep B low, the output sees parasitic capacitance from BOTH pmos devices, hence is the (...)
Hi, It has become necessary to perform hold analysis in worst case corner. I can think of 3 reasons: 1. Useful skew. If there is a large skew in the clock tree (e.g. to meet setup time), it is possible that this can cause a hold violation in worst corner, but not best corner 2. Negative setup and negative hold in (...)
Derating is normally used to "worsen" component values during design calculations to account for e.g. ageing. My guess is that the timing parameters are derated in this case, so that any timing calculations will use a worst case scenario.
in DC,it will use WLM to estimate the RC of the net and the delay calculation by the diffrent type the network : best case balance case or worst this situation will the DC calculate the net transition ?or it just use the output transition of driving cell for the input transition of fanout cell directly? in Pt ,when back (...)