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14 Threads found on edaboard.com: **Worst Case Calculation**

You are asking a lot of totally different questions.
1) The input impedance of your ADC has to be much greater than 13k (the impedance of your resistor string), or it WILL affect your reading. That's just a simple parallel resistance **calculation**. I would buffer it with an opamp.
2) **worst** **case** error will be about 1.9%. Assume all (...)

Analog Circuit Design :: 11-29-2014 23:08 :: barry :: Replies: **3** :: Views: **1056**

The sensitivity of any formula to a parameter is it's partial derivative.
- therefore use mean & % tolerances for linear analysis
So Vin = 6~17=11.5 +/- 5.5=11.5 +/- ~50% for sensitivity summations
Or use both **worst** **case** values ...

Power Electronics :: 10-27-2014 16:00 :: SunnySkyguy :: Replies: **2** :: Views: **554**

I will not trust online tools for optimization...Only basic component **calculation** and any compensation components **calculation** ( purely based on personal experience) will be best calculated by online tools ....Human intelligence is required and mandatory......Try to calculate the **worst** **case** current(Ripple and peak - mainly (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-22-2014 04:11 :: malli_1729 :: Replies: **6** :: Views: **1691**

I have designed a 16-bit modified radix-4 booth multiplier in cadence and simulated it using ADE (Analog Design Environment).
I wonder if there is any automatic method to calculate the **worst** **case** propagation delay of this circuit or I have to use a brute force method to find it?
As a matter of fact I don't have enough time to measure the delay of

ASIC Design Methodologies and Tools (Digital) :: 04-24-2014 20:12 :: nimoshy :: Replies: **0** :: Views: **1334**

Depending on the input pattern, one or both paths from input to output can get excited. For example, if B input stays at 1, and A input change from 0 to 1, then Z changes from 0 to 1. In this **case** the A to Z path is chosen. If both A and B change from 0 to 1, then both paths are chosen and i think the **worst** path (please double check this) from inpu

ASIC Design Methodologies and Tools (Digital) :: 10-16-2012 16:32 :: tariq786 :: Replies: **2** :: Views: **763**

you could use the **worst** **case** peak current per rail : Ipeak = Pmax / VDD
you can estimate the transient current (rule of thumb : Itransient ~ 0.5 * Imax)

PCB Routing Schematic Layout software and Simulation :: 04-30-2012 14:22 :: loosemoose :: Replies: **2** :: Views: **2338**

Hi All,
My small consulting company is moving into an industrial location since we are getting a used CNC milling machine. The machine takes 208V 3-Phase power, and the required current rating is 40 amps. I know that actual current usage depends on the load, but I'm trying to estimate the **worst** **case** scenario for the power usage of the machine.

Elementary Electronic Questions :: 01-23-2012 20:52 :: dksoba :: Replies: **0** :: Views: **589**

The size of your capacitor will be dependent on full or half wave bridge, **worst** **case** load and allowable ripple. As to limiting inrush current either a SCR bridge or diode bridge is used in conjunction to a current limiting resistor with a bypass, the bypass being energised when the voltage has stabilised to within 20% of full voltage. By limiting t

Power Electronics :: 01-13-2011 10:15 :: trekkytekky :: Replies: **4** :: Views: **2780**

Hi everyone,
The foundry usually will provide 3 libraries for synthesis: best **case**, **worst** **case** and typical **case**. Which one should I use for DC synthesis?
Besdies, in generating sdf, which librrary should be used also?
Thanks a lot
Tonyson

ASIC Design Methodologies and Tools (Digital) :: 11-22-2010 03:05 :: tonyson :: Replies: **1** :: Views: **657**

Hi, thank you for replying. I want to do a hand **calculation** of the NAND3 gate. I wish I can have the instantaneous, average as well as **worst** **case** power consumption. I also want to take the charge sharing effect into consideration. The transistor we use is nano scale transistor, so I doubt I can not use the square law of current equation (...)

Analog Circuit Design :: 07-27-2009 15:03 :: usa2005 :: Replies: **2** :: Views: **1190**

Here's some thoughts:
1) You need to look for **worst** **case** transitions. In a NOR gate, to switch low, **worst** **case** is only ONE nmos device pulling low (not two), hence one signal should stay low (while the other rises). If you keep B low, the output sees parasitic capacitance from BOTH pmos devices, hence is the (...)

Analog Circuit Design :: 06-06-2007 22:57 :: dipswitch :: Replies: **1** :: Views: **959**

Hi,
It has become necessary to perform hold analysis in **worst** **case** corner. I can think of 3 reasons:
1. Useful skew. If there is a large skew in the clock tree (e.g. to meet setup time), it is possible that this can cause a hold violation in **worst** corner, but not best corner
2. Negative setup and negative hold in (...)

ASIC Design Methodologies and Tools (Digital) :: 06-06-2006 03:46 :: leeenghan :: Replies: **6** :: Views: **3309**

Derating is normally used to "worsen" component values during design **calculation**s
to account for e.g. ageing.
My guess is that the timing parameters are derated in this **case**, so that any
timing **calculation**s will use a **worst** **case** scenario.

ASIC Design Methodologies and Tools (Digital) :: 07-10-2005 15:46 :: XNOX_Rambo :: Replies: **1** :: Views: **913**

in DC,it will use WLM to estimate the RC of the net and the delay **calculation** by the diffrent type the network : best **case** balance **case** or **worst** this situation will the DC calculate the net transition ?or it just use the output transition of driving cell for the input transition of fanout cell directly?
in Pt ,when back (...)

ASIC Design Methodologies and Tools (Digital) :: 07-09-2005 03:59 :: bendrift :: Replies: **0** :: Views: **999**

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core loss | duty cycle simulink | reverse and led | gcc compiler | solutions vlsi | timing drc | occurance | transmission line stub | ofdm matlab qam | constant factor