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80 Threads found on edaboard.com: Xilinx Fft
I am looking at the Altera DE0, DE1 and DE2 as well as the xilinx/Digilent university ranges of boards to try out some DSP programming. I also want to be able to process fft's. The issue appears to be which FPGA will do full floating point, or fixed floating point. I am not clear on the issues but my initial thoughts are to go for the Altera bo
I have never used this core, but looking at Pg84 says that there is a "Demonstration Test Bench" that comes with this core. Or is there any ready state machine design to control this fft core? The above TB simulation should give you hints as to
I am providing a voice signal to the cepstrum algorithm in xilinx system generator. Input is reaching fft7.1 properly but it is not generating any output. What I am having on scope is just 'x' undefined output. I also took help from the following link for fft7.1 He
Hi. I am using xilinx fft IP cores for fft transformation but the problem is that fft IP core takes fixed transformations length of 64,128,256,512,... is it possible to transform length of 50 , 100 , 126 etc. ie other than the available transform length of the iP core
hello everyone, i'm using a 256 fft core in matlab system generator, i have a bandpass signals from 750mhz to 1250mhz, im sampling at a rate of 1000mhz, for 750mhz im getting a 750mhz(single peak at 192 index value), for a 1000mhz im getting 0mhz, for 1110 im getting 110mhz, 1250 mhz i'm getting 250mhz, can anybody explain how pls??
can anybody tell me how much will be a delay for an n point fft in xilinx pipelined fft processor please??
Im working design 128point fft processor design in schematic using xilinx Pls help me to design for 128 point fft processor design need VHDL code
xilinx has IP cores that can do that for you. If you have xilinx ISE, open the core generator and choose one of the Logicore IP Fast Fourier Transform cores. The doc is here
6% of LUTs and 3% of registers? Are you sure this is for the 16K fft right? It's not a mistake and you posted a much smaller fft design? If this is the correct report, you're running into the issue I see a lot when utilization is very very low, bad placement. I'm surprised you even meet timing for lower sizes with utilization that low. To use pa
1) Put a known signal in and see if you get the proper output. 2) It most certainly is synthesizable. 3) What do you mean "how to use chipscope"? Do you have a specific question, or are you asking for a tutorial instead of reading the manual? 4) A digilink cable, as far as I know, is for some kind of network connection. I have no idea how it app
ERROR:Xst:1547 - C:/xilinx/bin/fft1/fft1.vhd line 8: Signal of type real is not supported. Come on now, really? The message is pretty self explanatory. Main code: library IEEE; use IEEE.std_logic_1164.all; use IEEE.MATH_REAL.ALL; package fft_pkg is type complex is
sir , i am finding it difficult to write code for 512 point fft processor using verilog please help me out
To start with, use xilinx IP for fft first and then you may try to create one yourself. Also as Tricky said, you should use Matlab design side by side for design.
hi, I am trying to generate IEEE 754 floating point Ifft using xilinx ipcores and verilog, but it is giving fft of the patterns as the answer, I tried by putting fft_inv=0 varying fwd_inv_we ='1' and then fwd_inv_we ='0' but i didnot get the proper answer. do anybody can help me solving the problem ..?
Hi If your main target is to make an fft block in actaul, then you have to do as achaleus says, but if your main task is something bigger and fft is just a part of it, and you are using xilinx then xilinx core generator will generate the fft block for you. It is much easier than doing things yourself and is (...)
Hi guys, I need some help to generate a 1024-point fft core on xilinx Virtex 6 FPGA. I have 32 incoming data samples per clock cycle but the xilinx fft IP core only support up to 12 channels which means the core only take 12 samples per clock cycle. I have tried increasing the clock frequency so that the (...)
hai friends i would like to run a basic fft code in c on an power pc which is created using xilinx EDK is it possible to do so , if so can can specify the procedure.
Hello! I'm dealing with the fft core from xilinx. What I would like to do is to take a real signal in input, perform its fft and then reconvert it into a real signal by doing its ifft. I'm facing a problem regarding the ifft. Actually, even if the output signal from the first fft block (...)
Hello! I'm facing the problem of simulating an fft core generator in vhdl. I have written a FSM and a test bench file to run the simulation of the xilinx fft core (Streaming) in ISE. I'm using a DDS module (from the core generator also) that generates a sinusoid at the input of the fft. What I'm getting at the (...)
Dear all, I have designed 8-point fft using xilinx IP core. I have selected floating point I/P and O/P options with Pipelined streaming I/O. I have written a sample testbench for 8-point input and I got some o/p. In general The back to back connection of Ifft and fft should give same results of I/P and O/P. (...)
Dear Miryama, Of course it depends on your design. How much bigger design are you using (including and fft)... The best way to know is to make one...U see as a proverb says, "when u do you understand" ...:) Then synthesize if you are using Altera or xilinx fpga, then Quartus and ISE will tell you how many resources have you used up. If excee
Dear all, I have design fixed point fft using Logic core and using xilinx ISE. I follow the following procedure I have given to fft several uniform data, different patterns of data like...32,16,32,16,32,16.... and I have verified the result through Matlab. They are correct. but when it comes to give sine wave signal. It i
From altera you want the cyclone series. They have plenty of onboard ram and embedded multipliers for your fft. xilinx would be the spartan or artix series.
Dear all, I have to design a system in which I am using the fft core using xilinx ISE CoreGen. Now my fft core works well and giving the output, but now I am not able to know that whether the output I am getting is correct or not. How can I get this confirmation that the Fast Fourier Transform of the values that I give is correct. (...)
By the way, download xilinx Document Navigator to manage all xilinx documents: Yup, pretty useful IMO. And unlike the earlier crap version, the current quite-acceptable version runs under wine too. :)
Hello, PBI bus data is 16bit binary. I would like to connect 16 bit binary data to input of xilinx fft logicore while fft core support only two'complement or single precision floting point format. I am not getting any idea how to use this core. how to convert 16 bit binary data in to single precision floting point format and how can i (...)
Logicore fft v7.1 - xilinx User Community Forums
The xilinx fft core is included with all editions of xilinx ISE. You can create a new fft core using the CORE Generator wizard. You should read, study, and understand the datasheet for the fft core, which can be accessed by clicking the datasheet button from within CORE Generator.
Regarding fft & Ifft CORE - xilinx User Community Forums Sir I am trying to use fft 5.0 core in xilinx10.1 as follows for 50 hz SinWAVE(THROUGH ADC)for noise removal 1. 64 Transform size 2. Radix-2 burst mode 3.I/p da
Sir I am trying to use fft 5.0 core in xilinx as follows for 50 hz SinWAVE(THROUGH ADC)for noise removal 1. 64 Transform size 2. Radix-2 burst mode 3.I/p data width 8 bit 4.Scaled 5. Natural order(without cylix prefix) I want to know what is the value of scale_sch. Further I want to use inverse fft for the O/P fft (...)
I know i can do that using xilinx IP Cores ,But how do i generate my own design file to compute the fft.
Please read and study XAPP199 - Writing Efficient Test Benches. Once you're comfortable with the construction of simple test benches, simulating the fft shouldn't be much of a problem.
Dear All, I realized an fft via IP CORE in xilinx Ise (virtex 5), the problem is that fft hasn't input enable! So I should have the entire stream of samples to elaborate one sample-per-clock (without missing spaces)! Without other cores when I hadn't samples available I simly put input_enable as '0' waiting for samples' availability. Now, (...)
any signal processing programs FIR Digital Filter (DSP Example) VHDL Tutorial: Learn by Example in xilinx ftp site their is fft code example...
Hello everyone, I used xilinx's core generator to create a fft block. How can I connect it to another vhdl script that I have written? Thanks in advance
plz help me on how to use ff v5 bcoz it is showing abnormal behaviour. i have tried other version that is working fine with same parameters but i have restriction to use fft v5 bcoz of cyclic prefix........ is there special treatment for fft v5?
Hi everyone I would like to implement key LTE baseband functions on xilinx FPGA device, such fft/Ifft functions. So I chose the xilinx fft core to do it. One big problem confusing me is that how to set the clock frequency of the fft core so that it could meet the requirements of the LTE (...)
Hello; I want to ask a few questions about performance of FPGA cores at high clock frequency. I'm trying to operate my system at 500 MHz. I will use fft core, dds core, FIR filter core of xilinx with my system. I can generate a system with the cores at 500 mhz succesfully on ISE 11.5; but I wonder if fft, DDS and FIR filters can (...)
hello can u say me plz how can we use matlab fo vhdl.. plz dont u have direct vhdl code which i can implement in xilinx ise environment.. thanking you..
So do it, whats the problem? I don't know how many LVDS pins Spartan-3E has, but remember to check it out. Also I would do fft also on FPGA because of FPGA parallelism - it would be fast enough. Check if You can get Spartan-3A, which has hardware multipliers. xilinx offers free fft core afaik, so no problem there, however 100MSPS is really (...)
Hi all after generating the fft core in xilinx ise , I found that comment on top of the file: " This file cannot be synthesized and should only be used with supported simulation tools." what does that means??
Hi all, I am trying to simulate xilinx fft core. I have calculated the bin size. But i do not know how to view that bin number in Modelsim. For example, If my input signal frequency is 10Hz, Sampling rate is 50, and fft point is 1024,my Bin size is 204.8. How do i see this with Modelsim. Please guide me. Thanks in advance Parvathi
I have created fft model using simulink xilinx block sets but i am not getting the output for the model. can anybody help me please. I am unable to attach the .mdl files. please tell me how to attach .mdl file
Dear ravics, Two approaches comes to mind: 1) CPU solution: instantiate a MicroBlaze CPU inside your xilinx FPGA, and find (google) some open source implementation of the STFT (written in C). Then compile it for Microblaze. 2) Non CPU solution, You probably would need a fft IP from xilinx, a BlockRAM memory (size depends on your (...)
I've installed xilinx 9.2i ISE software on my computer of 32 bit,windows xp operating system,sp-2-just as the software demands. I'm working with NCO and fft IP cores at my work place but when i install the same software on my pc,i'm unable to find the IP coregen option in the new source tab. Looks like my sir has used the same cd for installation
The xilinx core generator will make an fft module. You will have to create a "wrapper" to attach it to the MicroBlaze. I did something similar but ran out of time and didn't test the fft core with the MicroBlaze. I connected them using the Fast Simplex Links (FSLs).
Hi guys, fft is not my forte, and I'm considering fft core created by xilinx Core generator a black box. But here is what bugging me... I'm implementing FSM to compute 1024 point fft on audio sampled at 8000Hz. So, do I need to send data samples in chunks of 1024? And that for every 1024 read by the (...)
u can generate the core from xilinx xore generator or from Altera....
Hi All, Does anyone know how to map xilinx Libraries with QuestaSim. I have compiled xilinx Lib with "COMPLIB" command. But I don't know to map those Libraries with Questasim. If I simulate fft IP Core with Questasim , getting error like particular modules are missing . Kindly help me Thanks, Kumar
Hi dear Ahmad you could you xilinx cores for the fft and cyclic prefix for the OFDM system, also you could use PN generatot cores of CDMA. I used spartan 3A , it was good and cheap. if you want more details tell me.